1. 12 Jul, 2008 14 commits
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: Interrupt remapping infrastructure · 2ae21010
      Suresh Siddha authored
      Interrupt remapping (part of Intel Virtualization Tech for directed I/O)
      infrastructure.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      2ae21010
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: Queued invalidation infrastructure (part of VT-d) · fe962e90
      Suresh Siddha authored
      Queued invalidation (part of Intel Virtualization Technology for
      Directed I/O architecture) infrastructure.
      
      This will be used for invalidating the interrupt entry cache in the
      case of Interrupt-remapping and IOTLB invalidation in the case
      of DMA-remapping.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      fe962e90
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: move IOMMU_WAIT_OP() macro to intel-iommu.h · cf1337f0
      Suresh Siddha authored
      move IOMMU_WAIT_OP() macro to header file.
      
      This will be used by both DMA-remapping and Intr-remapping.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      cf1337f0
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: parse ioapic scope under vt-d structures · ad3ad3f6
      Suresh Siddha authored
      Parse the vt-d device scope structures to find the mapping between IO-APICs
      and the interrupt remapping hardware units.
      
      This will be used later for enabling Interrupt-remapping for IOAPIC devices.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      ad3ad3f6
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: Fix the need for RMRR in the DMA-remapping detection · 2d6b5f85
      Suresh Siddha authored
      Presence of RMRR structures is not compulsory for enabling DMA-remapping.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: default avatarYong Y Wang <yong.y.wang@intel.com>
      Cc: Yong Y Wang <yong.y.wang@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      2d6b5f85
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: use CONFIG_DMAR for DMA-remapping specific code · aaa9d1dd
      Suresh Siddha authored
      DMA remapping specific code covered with CONFIG_DMAR in
      the generic code which will also be used later for enabling Interrupt-remapping.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      aaa9d1dd
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: code re-structuring, to be used by both DMA and Interrupt remapping · 1886e8a9
      Suresh Siddha authored
      Allocate the iommu during the parse of DMA remapping hardware
      definition structures. And also, introduce routines for device
      scope initialization which will be explicitly called during
      dma-remapping initialization.
      
      These will be used for enabling interrupt remapping separately from the
      existing DMA-remapping enabling sequence.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      1886e8a9
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: fix the need for sequential array allocation of iommus · c42d9f32
      Suresh Siddha authored
      Clean up the intel-iommu code related to deferred iommu flush logic. There is
      no need to allocate all the iommu's as a sequential array.
      
      This will be used later in the interrupt-remapping patch series to
      allocate iommu much early and individually for each device remapping
      hardware unit.
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      c42d9f32
    • Suresh Siddha's avatar
      x64, x2apic/intr-remap: Intel vt-d, IOMMU code reorganization · e61d98d8
      Suresh Siddha authored
      code reorganization of the generic Intel vt-d parsing related routines and linux
      iommu routines specific to Intel vt-d.
      
      drivers/pci/dmar.c	now contains the generic vt-d parsing related routines
      drivers/pci/intel_iommu.c contains the iommu routines specific to vt-d
      Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      e61d98d8
    • Ingo Molnar's avatar
      Merge branch 'x86/core' into x86/x2apic · 1ba89386
      Ingo Molnar authored
      1ba89386
    • Ingo Molnar's avatar
      Merge branch 'linus' into x86/core · ae94b807
      Ingo Molnar authored
      Conflicts:
      
      	arch/x86/mm/ioremap.c
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      ae94b807
    • Roland McGrath's avatar
      x86_64: fix delayed signals · eca91e78
      Roland McGrath authored
      On three of the several paths in entry_64.S that call
      do_notify_resume() on the way back to user mode, we fail to properly
      check again for newly-arrived work that requires another call to
      do_notify_resume() before going to user mode.  These paths set the
      mask to check only _TIF_NEED_RESCHED, but this is wrong.  The other
      paths that lead to do_notify_resume() do this correctly already, and
      entry_32.S does it correctly in all cases.
      
      All paths back to user mode have to check all the _TIF_WORK_MASK
      flags at the last possible stage, with interrupts disabled.
      Otherwise, we miss any flags (TIF_SIGPENDING for example) that were
      set any time after we entered do_notify_resume().  More work flags
      can be set (or left set) synchronously inside do_notify_resume(), as
      TIF_SIGPENDING can be, or asynchronously by interrupts or other CPUs
      (which then send an asynchronous interrupt).
      
      There are many different scenarios that could hit this bug, most of
      them races.  The simplest one to demonstrate does not require any
      race: when one signal has done handler setup at the check before
      returning from a syscall, and there is another signal pending that
      should be handled.  The second signal's handler should interrupt the
      first signal handler before it actually starts (so the interrupted PC
      is still at the handler's entry point).  Instead, it runs away until
      the next kernel entry (next syscall, tick, etc).
      
      This test behaves correctly on 32-bit kernels, and fails on 64-bit
      (either 32-bit or 64-bit test binary).  With this fix, it works.
      
          #define _GNU_SOURCE
          #include <stdio.h>
          #include <signal.h>
          #include <string.h>
          #include <sys/ucontext.h>
      
          #ifndef REG_RIP
          #define REG_RIP REG_EIP
          #endif
      
          static sig_atomic_t hit1, hit2;
      
          static void
          handler (int sig, siginfo_t *info, void *ctx)
          {
            ucontext_t *uc = ctx;
      
            if ((void *) uc->uc_mcontext.gregs[REG_RIP] == &handler)
              {
                if (sig == SIGUSR1)
                  hit1 = 1;
                else
                  hit2 = 1;
              }
      
            printf ("%s at %#lx\n", strsignal (sig),
                    uc->uc_mcontext.gregs[REG_RIP]);
          }
      
          int
          main (void)
          {
            struct sigaction sa;
            sigset_t set;
      
            sigemptyset (&sa.sa_mask);
            sa.sa_flags = SA_SIGINFO;
            sa.sa_sigaction = &handler;
      
            if (sigaction (SIGUSR1, &sa, NULL)
                || sigaction (SIGUSR2, &sa, NULL))
              return 2;
      
            sigemptyset (&set);
            sigaddset (&set, SIGUSR1);
            sigaddset (&set, SIGUSR2);
            if (sigprocmask (SIG_BLOCK, &set, NULL))
              return 3;
      
            printf ("main at %p, handler at %p\n", &main, &handler);
      
            raise (SIGUSR1);
            raise (SIGUSR2);
      
            if (sigprocmask (SIG_UNBLOCK, &set, NULL))
              return 4;
      
            if (hit1 + hit2 == 1)
              {
                puts ("PASS");
                return 0;
              }
      
            puts ("FAIL");
            return 1;
          }
      Signed-off-by: default avatarRoland McGrath <roland@redhat.com>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      eca91e78
    • Rafael J. Wysocki's avatar
      x86: remove conflicting nx6325 and nx6125 quirks · da1f29f5
      Rafael J. Wysocki authored
      We have two conflicting DMA-based quirks in there for the same set of
      boxes (HP nx6325 and nx6125) and one of them actually breaks my box.
      
      So remove the extra code.
      Signed-off-by: default avatarRafael J. Wysocki <rjw@sisk.pl>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Cc: =?iso-8859-1?q?T=F6r=F6k_Edwin?= <edwintorok@gmail.com>
      Cc: Vegard Nossum <vegard.nossum@gmail.com>
      Cc: Andreas Herrmann <andreas.herrmann3@amd.com>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      da1f29f5
    • Linus Torvalds's avatar
  2. 11 Jul, 2008 26 commits