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  1. 28 Sep, 2007 4 commits
    • Paul Walmsley's avatar
      omap2 clock: add OMAP3430 clock definitions, basic code · 13c5f9d3
      Paul Walmsley authored 
      Define the clock tree, and add basic supporting clock code, for the
OMAP34xx chips.  The definitions and code go into two new files,
clock34xx.[ch].

The 34xx clock tree and code is written to reuse as much of the
existing OMAP clock infrastructure as is reasonable, and to introduce
the minimum amount possible of special-case code.  One notable
addition is the expansion of the dpll_params structure to include the
additional DPLL control registers used on OMAP34XX; most of these
extra registers are used in subsequent patches.

The patches seek to follow the TRM closely.  One implication of this
is that several intermediary clocks are defined that are not
software-controllable, and could normally be removed.  Some examples
include omap_96m_fck, core_l3_ick, corex2_fck.  I included these
clocks for several reasons.  Any further changes in pre-production
OMAP34xx silicon revisions may cause one of these clocks to become
software-controllable; the extra clocks make it easier to double-check
this patch against the TRM, if anyone wishes to do so; and ultimately,
it is easier to remove these clocks than to add them back in.  I
anticipate that we will remove these intermediary clocks once the 3430
silicon and clock definitions mature.

There are some notable divergences between the TRM and the patch.
They include:

* Clock suffixes end in "ck" rather than "clk"; this follows OMAP2
  clock naming style to minimize driver changes in the rest of the tree.

* The dpll*_alwon_fck clocks have been removed (they are not software
  controllable, and are unlikely to change)

* Some documentation in the TRM is inconsistent; I sought to apply
  the most likely resolution in the code.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      13c5f9d3
    • Paul Walmsley's avatar
      omap2 clock: add support for inverted enable bits · adb5ea75
      Paul Walmsley authored 
      On 3430ES2 (and presumably beyond), some clock tree branches from
DPLL3 & 4 can be powered down by setting 'PWRDN' bits in CM_CLKEN_PLL.
It appears that an easy way to power these branches down in our
existing clock framework is to use the PWRDN bits as clock enable bits
for the specific DPLL branches they affect.  The problem with this is
that the meaning of a set PWRDN bit is 'disable,' not 'enable.'  So,
introduce a new clock flag, INVERT_ENABLE, that clears the bit on
'clock enable,' and sets the bit on 'clock disable.'  This flag is used
on all PWRDN clock branches in the 3430 clock framework.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      adb5ea75
    • Paul Walmsley's avatar
      omap2 clock: split out OMAP2/3 common defines, clksel rates · 926865d2
      Paul Walmsley authored 
      This patch is a collection of minor clock code changes in preparation for
the OMAP3 clock merge.  Specifically:

* Since general-purpose timer and GFX module L3 clksel rates are common to
  OMAP2/3, hoist those into asm/arch/clock.h.

* Since the CM_FCLKEN define is common to OMAP2/3, remove the OMAP24XX_
  prefix.

* Designate the clock transaction code in clock.c as being OMAP2-specific.

* Fix a potential null pointer dereference that could occur when debugging
  is enabled in omap2_init_clksel_parent().  Clocks with no initially-defined
  parent (as is possible for clksel clocks) will trigger an oops due to a
  buggy conditional.

* Clean up omap2_wait_clock_ready().

* Remove unused struct dpll_params auto_idle* fields.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      926865d2
    • Paul Walmsley's avatar
      omap2 arch: fix CONTROL_DEVCONF addresses for OMAP3430 · e34c5653
      Paul Walmsley authored 
      OMAP3430 has two CONTROL_DEVCONF addresses, CONTROL_DEVCONF0 and
CONTROL_DEVCONF1; define them both.  Also, the existing address for
CONTROL_DEVCONF0 was incorrect; fix it.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      e34c5653
  3. 20 Sep, 2007 1 commit
  5. 19 Sep, 2007 35 commits