- 24 Apr, 2008 3 commits
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Sonic Zhang authored
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=4045 If adding timer in both timer handler and rx interrupt, a timer may be added when it is till in the pending list. Signed-off-by:
Sonic Zhang <sonic.zhang@analog.com> Signed-off-by:
Bryan Wu <cooloney@kernel.org>
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Mike Frysinger authored
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Mike Frysinger <vapier.adi@gmail.com> Signed-off-by:
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Graf Yang authored
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Graf Yang <graf.yang@analog.com> Signed-off-by:
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- 23 Apr, 2008 2 commits
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Sonic Zhang authored
Blackfin Serial Driver: Fix bug - kernel hangs when accessing uart 0 on bf537 when booting u-boot and linux on uart 1 Wait only when this UART is enabled. http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3995Signed-off-by:
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Mike Frysinger authored
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- 29 Feb, 2008 1 commit
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Graf Yang authored
Blackfin Serial Driver: Enable IR function when user application (irattach /dev/ttyBFx -s) call TIOCSETD ioctl with line discipline N_IRDA Signed-off-by:
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- 25 Apr, 2008 1 commit
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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- 24 Apr, 2008 18 commits
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Michael Hennerich authored
Signed-off-by:
Michael Hennerich <michael.hennerich@analog.com> Signed-off-by:
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Michael Hennerich authored
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Michael Hennerich authored
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Sonic Zhang authored
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Michael Hennerich authored
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Bernd Schmidt authored
Remove the circular buffering mechanism for exceptions. Instead, point RETX at a safe location from which to fetch three NOPs. This safe location is now in the fixed code area, and also used for certain anomaly workarounds, to ensure that user space can find a valid ICPLB when things are built with CONFIG_MPU. Also, save I/DCPLB_FAULT_ADDRESS when lowering to level 5, since the hardware reg is valid only at exception level. Signed-off-by:
Bernd Schmidt <bernds_cb1@t-online.de> Signed-off-by:
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Bernd Schmidt authored
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Graf Yang authored
[Blackfin] arch: fix bug - before assign new channel to the map register, need clear the bits first. http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=2445Signed-off-by:
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Graf Yang authored
- add platform device resources in board files - add new bfin_sir.h to each machines Signed-off-by:
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Mike Frysinger authored
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Robin Getz authored
[Blackfin] arch: try to remove condition that causes double fault, by checking current before it gets dereferenced Signed-off-by:
Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by:
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Sonic Zhang authored
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Robert P. J. Day authored
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Robert P. J. Day <rpjday@crashcourse.ca> Acked-by:
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Mike Frysinger authored
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Michael Hennerich authored
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Mike Frysinger authored
[Blackfin] arch: reorganize some of the board-customization options so that similar things are together and only available as needed Signed-off-by:
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Michael Hennerich authored
The irq setup code no longer calls gpio request and free. This patch also changes the default gpio_free behavior on Blackfin. A freed GPIO keeps it's last state, and is not defaulted back to an input. This is also what all other architectures do. Signed-off-by:
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Mike Frysinger authored
detect the memory available in the system on the fly by default rather than forcing people to set this manually in the kconfig Signed-off-by:
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- 23 Apr, 2008 15 commits
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Michael Hennerich authored
If the new value written to the PLL_CTL or VR_CTL register is the same as the previous value, the PLL wake-up will occur immediately (PLL is already locked), but the core and system clock will be bypassed for the PLL_LOCKCNT duration. For this interval, code will execute at the CLKIN rate instead of at the expected CCLK rate. Software should guard against this condition by comparing the current value to the new value before writing the new value. Signed-off-by:
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Mike Frysinger authored
[Blackfin] arch: add implicit icplb for the bootrom so we can use the utility functions in the kernel Signed-off-by:
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Grace Pan authored
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Grace Pan <grace.pan@analog.com> Signed-off-by:
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Mike Frysinger authored
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Mike Frysinger authored
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Sonic Zhang authored
[Blackfin] arch: fix bug - Section data_l1_cacheline_aligned should be defined in link script of kernel http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3978 Section data_l1_cacheline_aligned should be defined in link script of kernel, when L1 data sram bank A is not available. In bf536 with all data cache is enabled, there is no L1 data sram. Current link script won't define section data_l1.cacheline_aligned in this case. But, if user select put cacheline_aligned data into l1 sram in kernel menuconfig, these data will be dropped and access to these data will trigger data CPLB exception. Do panic in l1 relocation code as well. Signed-off-by:
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Robin Getz authored
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Mike Frysinger authored
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Mike Frysinger authored
- allow bootrom to be readable from supervisor mode - delete unused local variable "addr" - punt unused local defines of cplbinfo.c Signed-off-by:
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Bernd Schmidt authored
The DMA base registers are available in a global named "base_addr" for every Blackfin variant. Give this a more descriptive name, and remove duplicate tables from some drivers. Signed-off-by:
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Bernd Schmidt authored
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Bernd Schmidt authored
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Mike Frysinger authored
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Mike Frysinger authored
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Mike Frysinger authored
theres no need to declare ram{end,start,base} in the head.S files when declaring them with the other memory related variables in setup.c is so much simpler/nicer Signed-off-by:
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