- 25 Nov, 2009 36 commits
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Sekhar Nori authored
Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
This patch adds support for regulating the CVDD voltage for the DA850/OMAP-L138 platform. The CVDD min and max values for each OPP have been obtained from section 5.2 "Recommended Operating Conditions" of SPRS586 Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
Adds basic frequency scaling support for DA850/OMAP-L138. Currently, frequency scaling only on PLL0 is supported. No scaling of PLL1 as yet. Peripherals like MMC/SD which have a clock input synchronous with ARM clock will not work well since the clock will change behind their backs. Support for notification to such devices to adjust themselves to the new frequency will be added in later patches. Current defconfigs keep CPUFreq disabled so it will not affect normal operation. The OPP defintions assume clock input of 24MHz to the SoC. This is inline with hardcoding of input frequency in the <soc>.c files. At some point this will need to move into board dependent code as new boards appear with a different reference clock. Tested on OMAP-L138 EVM with ondemand governer and a shell script to vary processor load. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
Adds a basic CPUFreq driver for DaVinci devices registering with the kernel CPUFreq infrastructure. Support is added for both frequency and voltage regulation. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Kevin Hilman authored
All that is needed is the existing #include <linux/gpio.h> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Kevin Hilman authored
Newer revs of da830 silicon have different 'variant' field of the JTAG id register. Current code only supports rev 1.0 silicon. This patch adds support for rev1.1 and rev2.0 silicon and updates the 'name' strings to add a '-' between 'omap' & 'l137' to have consistent naming with da850/omap-l138. From Mark Grosen <mgrosen@ti.com>: "There are currently three silicon revisions for OMAPL137. The JTAG IDs (DEVIDR register contents) for each silicon revision are shown below: 0x0B7D F02F for silicon revision 1.0 0x8B7D F02F for silicon revision 1.1 0x9B7D F02F for silicon revision 2.0 Corresponding errata documentation will be available in the next few weeks on the ti.com website." Reported-by: Nick Thompson <Nick.Thompson@gefanuc.com> Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Kevin Hilman authored
The machine name string shows up in /proc/cpuinfo under 'Hardware' and can be used by userspace apps. Make the format consistent with the DA850/OMAP-l138 EVM by adding the '-' between OMAP and L137. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sergei Shtylyov authored
On this board the OHCI port's power control and over-current signals from TPS2065 power switch are connected via GPIO1[15] and GPIO2[1] respectively, so we can implement the DA8xx OHCI glue layer's hooks for overriding the root hub port's power and over-current status bits. We also have to properly set up the clocking mode in the CFGCHIP2 register, so that internal 24 MHz reference clock is fed to the USB 2.0 (MUSB) PHY and its output is used to clock the USB 1.1 (OHCI) PHY... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sergei Shtylyov authored
Add the function to register the OHCI platform device, given the root hub related platform data passed from the board specific code. The platfrom data provide for overriding the OHCI port power and over-current bits at the board level. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sergei Shtylyov authored
These are needed by the MUSB and OHCI glue layers... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sandeep Paulraj authored
The patch itself does not change the functionality of any existing code. PARAM entries in the present GIT kernel are referred to as slots. New API's being added to the EDMA driver were referring to these PARAM entries as "params". This patch updates the terminolgy used in the EDMA driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sandeep Paulraj authored
The reserve_contiguous_params function is used to reserve a set of contiguous PARAMs. If we do not find a complete set of contiguous PARAMs, the functions still has to free every PARAM that it found to be free in the process of finding a complete set and thus marked as "in use". This patch mainly deals with correctly handling the freeing of PARAMs. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sneha Narnakaje authored
This patch updates the NAND driver platform data to use 4-bit ECC and the ECC_HW/ECC_HW_OOB_FIRST modes. Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sneha Narnakaje authored
This patch updates the NAND driver platform data to use 4-bit ECC and the ECC_HW/ECC_HW_OOB_FIRST modes. Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sandeep Paulraj authored
The edma_alloc_cont_slots API is used for obtaining a set of contiguous slots. When we use the "_ANY" option with this API, by definition of this option it is suppossed to start looking for a set of contiguous slots starting from slot 64 for DaVinci SOC's and 32 for DA8xx SOC's. This has been explained in the API description in the driver itself. So when we use the "_ANY" option with this API, the slot number passed as an argument should be a "don't care". This patch takes care of this condition mentioned above. When checking to see if the starting slot is a valid number, it checks to make sure that the "_ANY" option is not used. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sandeep Paulraj authored
In the edma_free_cont_slots API, the variable slot was being modified and then used in the for loop. This results in incorrect behaviour when the API is used. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sudhakar Rajashekhara authored
On the latest DA850/OMAP-L138 EVM (Beta) the GPIO pin number of LCD panel power has changed. This patch takes care of this change. Software will support only Beta versions of DA850/OMAP-L138 EVM. In the process, add the missing entry for data pin 0 and remove the GPIO specific pins from da850_lcdcntl_pins structure. EVM specific muxing for LCD is being done in the board file now. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Mark A. Greer authored
Add RTC support for the da830/omap-l137 and da850/omap-l138 SoC's by leveraging existing the rtc-omap driver. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Steve Chen authored
Add graphics support for the Sharp LCD035Q3DG01 graphical LCD that's on the User Interface (UI) daughter card of the DA830/OMAP-L137 EVM. The LCD shares EMIFA lines with the NAND and NOR devices that are also on the UI card so those lines are shared via a couple of muxes. The muxes are controlled by the 'MUX_MODE' line on the UI card. The 'MUX_MODE' line is controlled by pin P6 of a pcf8574 i2c expander that's at i2c address 0x3f on UI card. The i2c expander is controlled using the gpio infrastructure from the board code using the 'setup()' and 'teardown()' routines. Signed-off-by: Steve Chen <schen@mvista.com> Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Mark A. Greer authored
Add support for the Sharp LCD035Q3DG01 graphical LCD. This requires a minor interface change to da8xx_register_lcdc() so that the board code can pass in the platform_data which describes the lcd controller that's to be used. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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David A. Griego authored
Add pinmux settings, etc. to enable the MMC/SC hardware. Signed-off-by: David A. Griego <dgriego@mvista.com> Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Hemant Pedanekar authored
DM6467 silicon revisions 3.x have variant field in JTAGID register as '1'. This path adds entry for the same in dm646x_ids to be able to boot on boards with 3.x revision chips. Also modifies name for 'variant=0' (revisions 1.0, 1.1). Signed-off-by: Hemant Pedanekar <hemantp@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
The patch allows Async3 clock source to be selected between PLL1 SYSCLK2 and PLL0 SYSCLK2. Having Async3 source from PLL1 SYSCLK2 allows peripherals on that domain to remain unaffected by frequency scaling on PLL0. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
The clk_set_parent() API is implemented to enable re-parenting clocks in the clock tree. This is useful in DVFS and helps by shifting clocks to an asynchronous domain where supported by hardware Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
clk_round_rate, clk_set_rate have been updated to handle dynamic frequency changes. The motivation behind the changes is to support dynamic CPU frequency change. davinci_set_pllrate() changes the PLL rate of a given PLL. This function has been presented as a generic function though it has been tested only on OMAP-L138 EVM. No other currently available DaVinci device will probably use this function, but any future device specific changes will hopefully be small enough to get taken care using a cpu_is_xxx() macro. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
Make clock rate recalculation easy by having a re-calculate function for each clock. The existing functions for calculation of output rates of PLL and PLL-derived sysclks have been convered to the new re-calculate API. A new function is introduced to take care of rate (re)calculation for leaf clocks. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
Achieve easy top down traversal of clock tree by keeping track of each clock's list of children. This is useful in supporting DVFS where clock rates of all children need to be updated in an efficient manner. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
This makes it clear that JTAG ID register is part of the SYSCFG module Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
Avoid use of IO_ADDRESS() for SYSCFG module by doing an ioremap() instead. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sekhar Nori authored
Rename the DA8XX_BOOT_CFG_BASE macro to get it in line with the public documentation for these parts. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Mark A. Greer authored
The DA830/OMAP-L137 EVM cannot use the default pinmux setup for McASP1 so put the correct settings in the board file for that platform. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Mark A. Greer authored
For consistency with existing code, change the name of da8xx_init_mcasp() to da8xx_register_mcasp(). Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Mark A. Greer authored
Some mcasp code was inserted between the emac resource setup and the related register routine that registers the emac. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Miguel Aguilar authored
1) Registers the platform device for McBSP on dm365. 2) Add platform data to DM365 EVM board file. 3) Set i2c address for audio codec at DM365 EVM board file. Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Sandeep Paulraj authored
The parent clock for the USB source clock is actually PLL1 aux clock, not PLL2 sysclk1. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Phaneendra Kumar authored
This patch fixes a typo/bug in the DM365 SDIO interrupt assignment Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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- 19 Nov, 2009 4 commits
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Linus Torvalds authored
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git://git.linux-nfs.org/projects/trondmy/nfs-2.6Linus Torvalds authored
* 'bugfixes' of git://git.linux-nfs.org/projects/trondmy/nfs-2.6: SUNRPC: Address buffer overrun in rpc_uaddr2sockaddr() NFSv4: Fix a cache validation bug which causes getcwd() to return ENOENT
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Alan Cox authored
As this struct is exposed to user space and the API was added for this release it's a bit of a pain for the C++ world and we still have time to fix it. Rename the fields before we end up with that pain in an actual release. Signed-off-by: Alan Cox <alan@linux.intel.com> Reported-by: Olivier Goffart Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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David Woodhouse authored
Commit 86cf898e ("intel-iommu: Check for 'DMAR at zero' BIOS error earlier.") was supposed to work by pretending not to detect an IOMMU if it was actually being reported by the BIOS at physical address zero. However, the intel_iommu_init() function is called unconditionally, as are the corresponding functions for other IOMMU hardware. So the patch only worked if you have RAM above the 4GiB boundary. It caused swiotlb to be initialised when no IOMMU was detected during early boot, and thus the later IOMMU init would refuse to run. But if you have less RAM than that, swiotlb wouldn't get set up and the IOMMU _would_ still end up being initialised, even though we never claimed to detect it. This patch also sets the dmar_disabled flag when the error is detected during the initial detection phase -- so that the later call to intel_iommu_init() will return without doing anything, regardless of whether swiotlb is used or not. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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