- 12 Sep, 2005 40 commits
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Andi Kleen authored
It only offers extremly dubious security advantages and is not worth the overhead in this critical path. Signed-off-by:
Andi Kleen <ak@suse.de> Signed-off-by:
Linus Torvalds <torvalds@osdl.org>
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Andi Kleen authored
(from i386) Signed-off-by:
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Andi Kleen authored
The global bit was not set in the first 2MB page, instead it had a bit in the free AVL section which is useless. Fixed thus. Noticed by Eric Biederman Cc: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by:
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Hugh Dickins authored
x86_64 idle=poll might be a little less responsive than it should: unlike mwait_idle, and unlike i386, its poll_idle left TIF_POLLING_NRFLAG set. Signed-off-by:
Hugh Dickins <hugh@veritas.com> Signed-off-by:
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Andi Kleen authored
Saves some memory except for hotplug situations. Signed-off-by:
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Andi Kleen authored
The generic TLB flush functions kept upto 506 pages per CPU to avoid too frequent IPIs. This value was done for the L1 cache of older x86 CPUs, but with modern CPUs it does not make much sense anymore. TLB flushing is slow enough that using the L2 cache is fine. This patch increases the flush array on x86-64 to cache 5350 pages. That is roughly 20MB with 4K pages. It speeds up large munmaps in multithreaded processes on SMP considerably. The cost is roughly 42k of memory per CPU, which is reasonable. I only increased it on x86-64 for now, but it would probably make sense to increase it everywhere. Embedded architectures with SMP may keep it smaller to save some memory per CPU. Signed-off-by:
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Andi Kleen authored
asm-x86-64/timex.h does not reference CONFIG constants. Do not need to include config.h. Signed-off-by:
Grant Grundler <iod00d@hp.com> Signed-off-by:
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Andi Kleen authored
- Remove unused irqrsp field - Remove pda->me - Optimize set_softirq_pending slightly Signed-off-by:
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Andi Kleen authored
This adds console and earlyprintk support for a host file on AMD's SimNow simulator. Signed-off-by:
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Andi Kleen authored
Instead of using a global spinlock to protect the state of the remote TLB flush use a lock and state for each sending CPU. To tell the receiver where to look for the state use 8 different call vectors. Each CPU uses a specific vector to trigger flushes on other CPUs. Depending on the received vector the target CPUs look into the right per cpu variable for the flush data. When the system has more than 8 CPUs they are hashed to the 8 available vectors. The limited global vector space forces us to this right now. In future when interrupts are split into per CPU domains this could be fixed, at the cost of needing more IPIs in flat mode. Also some minor cleanup in the smp flush code and remove some outdated debug code. Requires patch to move cpu_possible_map setup earlier. Signed-off-by:
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Tsuneo.Yoshioka@f-secure.com authored
If we use 64bit kernel on ia64/x86_64/s390 architecture, and we run 32bit binary on 32bit compatibility mode, sendfile system call seems be not set offset argument. This is because sendfile's return value is not zero but the code regards the result by return value is zero or not. This problem will be affect to ia64/x86_64/s390 and not affect to other architecture does not affect other architecture (mips/parisc/ppc64/sparc64). Signed-off-by:
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Andi Kleen authored
Include build number in oops output Helps me to match oopses to correct kernel. Signed-off-by:
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Andi Kleen authored
Since this is shared code I had to implement it for i386 too Signed-off-by:
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Andi Kleen authored
The resume code uses CPU hotplug now so at resume time we only ever see one CPU. Pointed out by Yu Luming. Signed-off-by:
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Andi Kleen authored
The FLATMEM people added it, but there doesn't seem a good reason because end_pfn is identical. Signed-off-by:
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Andi Kleen authored
Avoids a very dumb loop Signed-off-by:
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Andi Kleen authored
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Andi Kleen authored
Use pcibus_to_node directly Signed-off-by:
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Andi Kleen authored
It could be wrong for kexec or other cases. Read it from the CPU instead. Signed-off-by:
Murali <muralim@in.ibm.com> Signed-off-by:
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Andi Kleen authored
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Andi Kleen authored
One machine is constantly throwing NMI watchdog timeouts in mce_log This was one attempt to fix it. (AK: this doesn't actually fix the bug I'm seeing unfortunately, probably drop. I don't like it that the reader can spin forever now waiting for a writer) Signed-off-by:
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Andi Kleen authored
It's already handled in the main swiotlb code. Signed-off-by:
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Andi Kleen authored
No-one needs it then Signed-off-by:
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Andi Kleen authored
This leads to bootmem allocating first from node 0 instead of from the last node. This avoids swiotlb allocating on the last node, which doesn't really work on a machine with >4GB. Note: there is a better patch around from someone else that gets rid of the pgdat list completely. Signed-off-by:
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Andi Kleen authored
PCI_DMA_BUS_IS_PHYS has to be zero even when the GART IOMMU is disabled and the swiotlb is used. Otherwise the block layer does unnecessary double bouncing. Signed-off-by:
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Andi Kleen authored
Originally from Stuart Hayes. When setting up the APIC for the Uniprocessor kernel don't assume the CPU has an APIC ID of zero. This fixes boot with the UP kernel on Dell PowerEdge 6800/6850 4way systems. Cc: Stuart.Hayes@dell.com Signed-off-by:
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Andi Kleen authored
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Andi Kleen authored
In particular on systems where the local APIC space and node space is very different from the Linux CPU number space. Previously the older NUMA setup code directly parsing the K8 northbridge registers had some issues on 8 socket or dual core systems. This patch fixes them. This is mainly done by fixing some confusion between Linux CPU numbers and local APIC ids. We now pass the local APIC IDs to later code, which avoids mismatches. Also add some heuristics to detect cases where the Hypertransport nodeids and the local APIC IDs don't match, but are shifted by a constant offset. This is still all quite hackish, hopefully BIOS writers fill in correct SRATs instead. Signed-off-by:
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Andi Kleen authored
Suggested by someone I forgot who sorry. Signed-off-by:
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Andi Kleen authored
Signed-off-by:
Suresh Sidda <suresh.b.siddha@intel.com> Signed-off-by:
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Andi Kleen authored
Do that later when the CPU boots. SRAT just stores the APIC<->Node mapping node. This fixes problems on systems where the order of SRAT entries does not match the MADT. Signed-off-by:
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Andi Kleen authored
No functional changes Signed-off-by:
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Andi Kleen authored
We used to disable them to work around a bug, but that is not needed anymore. Keeping them enabled avoids the NMI watchdog triggering in some cases. Signed-off-by:
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Andi Kleen authored
Handles case where BIOS gives CPUs very large APIC numbers correctly. Signed-off-by:
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Andi Kleen authored
No x86-64 chipset has these APICs. Signed-off-by:
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Andi Kleen authored
This was just needed for the Numasaurus, which fortunately doesn't support x86-64 CPUs. Signed-off-by:
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Andi Kleen authored
No x86-64 chipset has this bug Generated code doesn't change because it was always disabled. Signed-off-by:
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Andi Kleen authored
We don't do workarounds for ancient hardware bugs. Signed-off-by:
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Andi Kleen authored
Allow diskless booting. Signed-off-by:
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Andi Kleen authored
Now that Greg implemented MCFG/_SEG support this shouldn't be needed anymore Cc: gregkh@suse.de Signed-off-by:
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