1. 22 May, 2006 1 commit
  2. 21 May, 2006 14 commits
  3. 20 May, 2006 9 commits
  4. 19 May, 2006 1 commit
  5. 18 May, 2006 2 commits
    • David Woodhouse's avatar
      [JFFS2] Support new device nodes · aef9ab47
      David Woodhouse authored
      Device node major/minor numbers are just stored in the payload of a single
      data node. Just extend that to 4 bytes and use new_encode_dev() for it.
      
      We only use the 4-byte format if we _need_ to, if !old_valid_dev(foo).
      This preserves backwards compatibility with older code as much as
      possible. If we do make devices with major or minor numbers above 255, and
      then mount the file system with the old code, it'll just read the first
      two bytes and get the numbers wrong. If it comes to garbage-collect it,
      it'll then write back those wrong numbers. But that's about the best we
      can expect.
      Signed-off-by: default avatarDavid Woodhouse <dwmw2@infradead.org>
      aef9ab47
    • KaiGai Kohei's avatar
      Merge git://git.infradead.org/mtd-2.6 · 20a92fc7
      KaiGai Kohei authored
      20a92fc7
  6. 17 May, 2006 11 commits
  7. 16 May, 2006 2 commits
    • David Woodhouse's avatar
      [JFFS2] Repack some on-medium structures. ARM is weirder than I thought. · ba9627b8
      David Woodhouse authored
      We have to pack at least the jint16_t structure, because otherwise it'll
      be four bytes in size. Thankfully, we can do that and _not_ pack the
      actual node structures, and the compiler still doesn't emit stupid code.
      Signed-off-by: default avatarDavid Woodhouse <dwmw2@infradead.org>
      ba9627b8
    • Sergei Shtylyov's avatar
      NAND: Fix NAND ECC errors on AMD Au1550 · 35af68b5
      Sergei Shtylyov authored
          On AMD Au1550 the static bus controller fails to keep -CE asserted during
      chip ready delay on read commands and the NAND chip being used requires this.
      So, the current driver allows nand_base.c to drive -CE manually during the
      entire sector read. When the PCMCIA driver is enabled however, occasionally
      the ECC errors occur on NAND reads. This happens because the PCMCIA driver
      polls sockets periodically and reads one of the board's control/status regs
      (BCSRs) which are on the same static bus as the NAND flash, and just use
      another chip select (and the NOR flash also resides on that bus), so as the
      NAND driver forces NAND chip select asserted and the -RE signal is shared, a
      contention occurs on the static bus when BCSR or NOR flash is read while we're
      reading from NAND.
          So, we either can't keep interrupts enabled during the whole NAND sector
      read (which is hardly acceptable), or have to implement some interlocking
      scheme between multiple drivers (which is painful, and makes me shudder :-).
          There's a third way which has proven to work: to force -CE asserted only
      while we're waiting for a NAND chip to become ready after a read command,
      disabling interrupts for a maximum of 25 microseconds (according to Toshiba
      TC58DVM92A1FT00 datasheet -- this chip is mentioned in the board schematics);
      for Samsung NAND chip which seems to be actually used this delay is even less,
      12 us.
      Signed-off-by: default avatarKonstantin Baydarov <kbaidarov@ru.mvista.com>
      Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
      Signed-off-by: default avatarDavid Woodhouse <dwmw2@infradead.org>
      35af68b5