Processor deadlock when a false hazard is created on Cortex-A8

This patch adds a workaround for the 458692 Cortex-A8 (r2p0)
erratum. It sets the corresponding bits in the auxiliary control
register so that the PLD instruction becomes a NOP.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

arch/arm/Kconfig

@@ -563,6 +563,18 @@ config ARM_ERRATA_430973
 	  prediction. This results in Cortex-A8 executing the new code
 	  sequence in the incorrect ARM or Thumb state.
 
+config ARM_ERRATA_458693
+	bool "Processor deadlock when a false hazard is created on Cortex-A8"
+	depends on CPU_V7
+	default n
+	help
+	  This option enables the workaround for the 458692 Cortex-A8
+	  (r2p0) erratum. For very specific sequences of memory
+	  operations, it is possible for a hazard condition intended
+	  for a cache line to instead be incorrectly associated with a
+	  different cache line. This false hazard might then cause a
+	  processor deadlock.
+
 endmenu
 
 source "arch/arm/common/Kconfig"

arch/arm/mm/proc-v7.S

@@ -191,6 +191,12 @@ __v7_setup:
 	mrc	p15, 0, r10, c1, c0, 1		@ read aux control register
 	orr	r10, r10, #(1 << 6)		@ set IBE to 1
 	mcr	p15, 0, r10, c1, c0, 1		@ write aux control register
+#endif
+#ifdef CONFIG_ARM_ERRATA_458693
+	mrc	p15, 0, r10, c1, c0, 1		@ read aux control register
+	orr	r10, r10, #(1 << 5)		@ set L1NEON to 1
+	orr	r10, r10, #(1 << 9)		@ set PLDNOP to 1
+	mcr	p15, 0, r10, c1, c0, 1		@ write aux control register
 #endif
 	mov	r10, #0
 #ifdef HARVARD_CACHE