Commit f8b201fc authored by Mark Langsdorf's avatar Mark Langsdorf Committed by Ingo Molnar

x86: cacheinfo: replace sysfs interface for cache_disable feature

Impact: replace sysfs attribute

Current interface violates against "one-value-per-sysfs-attribute
rule". This patch replaces current attribute with two attributes --
one for each L3 Cache Index Disable register.
Signed-off-by: default avatarMark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: default avatarAndreas Herrmann <andreas.herrmann3@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
LKML-Reference: <20090409131849.GJ31527@alberich.amd.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent afd9fcee
...@@ -697,73 +697,69 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) ...@@ -697,73 +697,69 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
#define to_object(k) container_of(k, struct _index_kobject, kobj) #define to_object(k) container_of(k, struct _index_kobject, kobj)
#define to_attr(a) container_of(a, struct _cache_attr, attr) #define to_attr(a) container_of(a, struct _cache_attr, attr)
static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf) static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
unsigned int index)
{ {
const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map); int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
int node = cpu_to_node(cpumask_first(mask)); int node = cpu_to_node(cpu);
struct pci_dev *dev = NULL; struct pci_dev *dev = node_to_k8_nb_misc(node);
ssize_t ret = 0; unsigned int reg = 0;
int i;
if (!this_leaf->can_disable) if (!this_leaf->can_disable)
return sprintf(buf, "Feature not enabled\n");
dev = node_to_k8_nb_misc(node);
if (!dev) {
printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
return -EINVAL; return -EINVAL;
}
for (i = 0; i < 2; i++) { if (!dev)
unsigned int reg; return -EINVAL;
pci_read_config_dword(dev, 0x1BC + i * 4, &reg); pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
return sprintf(buf, "%x\n", reg);
}
ret += sprintf(buf, "%sEntry: %d\n", buf, i); #define SHOW_CACHE_DISABLE(index) \
ret += sprintf(buf, "%sReads: %s\tNew Entries: %s\n", static ssize_t \
buf, show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \
reg & 0x80000000 ? "Disabled" : "Allowed", { \
reg & 0x40000000 ? "Disabled" : "Allowed"); return show_cache_disable(this_leaf, buf, index); \
ret += sprintf(buf, "%sSubCache: %x\tIndex: %x\n",
buf, (reg & 0x30000) >> 16, reg & 0xfff);
}
return ret;
} }
SHOW_CACHE_DISABLE(0)
SHOW_CACHE_DISABLE(1)
static ssize_t static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
store_cache_disable(struct _cpuid4_info *this_leaf, const char *buf, const char *buf, size_t count, unsigned int index)
size_t count)
{ {
const struct cpumask *mask = to_cpumask(this_leaf->shared_cpu_map); int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
int node = cpu_to_node(cpumask_first(mask)); int node = cpu_to_node(cpu);
struct pci_dev *dev = NULL; struct pci_dev *dev = node_to_k8_nb_misc(node);
unsigned int ret, index, val; unsigned long val = 0;
if (!this_leaf->can_disable) if (!this_leaf->can_disable)
return -EINVAL; return -EINVAL;
if (strlen(buf) > 15) if (!capable(CAP_SYS_ADMIN))
return -EINVAL; return -EPERM;
ret = sscanf(buf, "%x %x", &index, &val); if (!dev)
if (ret != 2)
return -EINVAL;
if (index > 1)
return -EINVAL; return -EINVAL;
val |= 0xc0000000; if (strict_strtoul(buf, 10, &val) < 0)
dev = node_to_k8_nb_misc(node);
if (!dev) {
printk(KERN_ERR "Attempting AMD northbridge operation on a system with no northbridge\n");
return -EINVAL; return -EINVAL;
}
val |= 0xc0000000;
pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000); pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
wbinvd(); wbinvd();
pci_write_config_dword(dev, 0x1BC + index * 4, val); pci_write_config_dword(dev, 0x1BC + index * 4, val);
return count;
}
return 1; #define STORE_CACHE_DISABLE(index) \
static ssize_t \
store_cache_disable_##index(struct _cpuid4_info *this_leaf, \
const char *buf, size_t count) \
{ \
return store_cache_disable(this_leaf, buf, count, index); \
} }
STORE_CACHE_DISABLE(0)
STORE_CACHE_DISABLE(1)
struct _cache_attr { struct _cache_attr {
struct attribute attr; struct attribute attr;
...@@ -785,7 +781,10 @@ define_one_ro(size); ...@@ -785,7 +781,10 @@ define_one_ro(size);
define_one_ro(shared_cpu_map); define_one_ro(shared_cpu_map);
define_one_ro(shared_cpu_list); define_one_ro(shared_cpu_list);
static struct _cache_attr cache_disable = __ATTR(cache_disable, 0644, show_cache_disable, store_cache_disable); static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
show_cache_disable_0, store_cache_disable_0);
static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
show_cache_disable_1, store_cache_disable_1);
static struct attribute * default_attrs[] = { static struct attribute * default_attrs[] = {
&type.attr, &type.attr,
...@@ -797,7 +796,8 @@ static struct attribute * default_attrs[] = { ...@@ -797,7 +796,8 @@ static struct attribute * default_attrs[] = {
&size.attr, &size.attr,
&shared_cpu_map.attr, &shared_cpu_map.attr,
&shared_cpu_list.attr, &shared_cpu_list.attr,
&cache_disable.attr, &cache_disable_0.attr,
&cache_disable_1.attr,
NULL NULL
}; };
......
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