Commit f0d6570e authored by Andrea Shepard's avatar Andrea Shepard Committed by Greg Kroah-Hartman

sparc64: Fix race in arch/sparc64/kernel/trampoline.S

[ Upstream commit e0037df3 ]

Make arch/sparc64/kernel/trampoline.S in 2.6.27.1 lock prom_entry_lock
when calling the PROM.  This prevents a race condition that I observed
causing a hang on startup on a 12-CPU E4500.

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Signed-off-by: default avatarAndrea Shepard <andrea@persephoneslair.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 0cba8ac1
...@@ -328,6 +328,12 @@ after_lock_tlb: ...@@ -328,6 +328,12 @@ after_lock_tlb:
wrpr %g0, 0, %wstate wrpr %g0, 0, %wstate
sethi %hi(prom_entry_lock), %g2
1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
membar #StoreLoad | #StoreStore
brnz,pn %g1, 1b
nop
/* As a hack, put &init_thread_union into %g6. /* As a hack, put &init_thread_union into %g6.
* prom_world() loads from here to restore the %asi * prom_world() loads from here to restore the %asi
* register. * register.
...@@ -337,7 +343,7 @@ after_lock_tlb: ...@@ -337,7 +343,7 @@ after_lock_tlb:
sethi %hi(is_sun4v), %o0 sethi %hi(is_sun4v), %o0
lduw [%o0 + %lo(is_sun4v)], %o0 lduw [%o0 + %lo(is_sun4v)], %o0
brz,pt %o0, 1f brz,pt %o0, 2f
nop nop
TRAP_LOAD_TRAP_BLOCK(%g2, %g3) TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
...@@ -369,10 +375,10 @@ after_lock_tlb: ...@@ -369,10 +375,10 @@ after_lock_tlb:
call %o1 call %o1
add %sp, (2047 + 128), %o0 add %sp, (2047 + 128), %o0
ba,pt %xcc, 2f ba,pt %xcc, 3f
nop nop
1: sethi %hi(sparc64_ttable_tl0), %o0 2: sethi %hi(sparc64_ttable_tl0), %o0
set prom_set_trap_table_name, %g2 set prom_set_trap_table_name, %g2
stx %g2, [%sp + 2047 + 128 + 0x00] stx %g2, [%sp + 2047 + 128 + 0x00]
mov 1, %g2 mov 1, %g2
...@@ -386,7 +392,11 @@ after_lock_tlb: ...@@ -386,7 +392,11 @@ after_lock_tlb:
call %o1 call %o1
add %sp, (2047 + 128), %o0 add %sp, (2047 + 128), %o0
2: ldx [%l0], %g6 3: sethi %hi(prom_entry_lock), %g2
stb %g0, [%g2 + %lo(prom_entry_lock)]
membar #StoreStore | #StoreLoad
ldx [%l0], %g6
ldx [%g6 + TI_TASK], %g4 ldx [%g6 + TI_TASK], %g4
mov 1, %g5 mov 1, %g5
......
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