Commit e9ea6124 authored by Paul Walmsley's avatar Paul Walmsley Committed by Tony Lindgren

OMAP3 clock: fix dss1_alwon_fck

Commit a63efb15 broke the dss1_alwon_fck
clock enable on 3430ES2+.  The clock code was not waiting for the module
to come out of idle.

Problem reported by Rajendra Nayak <rnayak@ti.com>.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 13d97456
...@@ -2304,7 +2304,7 @@ static struct clk dss1_alwon_fck_3430es1 = { ...@@ -2304,7 +2304,7 @@ static struct clk dss1_alwon_fck_3430es1 = {
.prcm_mod = OMAP3430_DSS_MOD, .prcm_mod = OMAP3430_DSS_MOD,
.enable_reg = CM_FCLKEN, .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_DSS1_SHIFT, .enable_bit = OMAP3430_EN_DSS1_SHIFT,
.flags = CLOCK_IN_OMAP343X, .flags = CLOCK_IN_OMAP3430ES1,
.clkdm = { .name = "dss_clkdm" }, .clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
...@@ -2317,7 +2317,7 @@ static struct clk dss1_alwon_fck_3430es2 = { ...@@ -2317,7 +2317,7 @@ static struct clk dss1_alwon_fck_3430es2 = {
.enable_reg = CM_FCLKEN, .enable_reg = CM_FCLKEN,
.enable_bit = OMAP3430_EN_DSS1_SHIFT, .enable_bit = OMAP3430_EN_DSS1_SHIFT,
.idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, .idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
.flags = CLOCK_IN_OMAP343X | WAIT_READY, .flags = CLOCK_IN_OMAP3430ES2 | WAIT_READY,
.clkdm = { .name = "dss_clkdm" }, .clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
......
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