Mark repetitive Jazelle data aborts as writes

The FSR bit 11 is not set by a memory write causing a data abort while
in Jazelle state, making the copy-on-write mechanism unusable. This
workaround marks repetitive Jazelle data aborts on the same address as
write aborts.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

arch/arm/kernel/asm-offsets.c

@@ -67,6 +67,7 @@ int main(void)
 #ifdef CONFIG_CRUNCH
   DEFINE(TI_CRUNCH_STATE,	offsetof(struct thread_info, crunchstate));
 #endif
+  DEFINE(TI_JABORT_ADDR,	offsetof(struct thread_info, jabort_addr));
   BLANK();
   DEFINE(S_R0,			offsetof(struct pt_regs, ARM_r0));
   DEFINE(S_R1,			offsetof(struct pt_regs, ARM_r1));

arch/arm/mm/abort-ev5tj.S

 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <asm/asm-offsets.h>
 #include "abort-macro.S"
 /*
  * Function: v5tj_early_abort
@@ -24,7 +25,7 @@ ENTRY(v5tj_early_abort)
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
 	bic	r1, r1, #1 << 11 | 1 << 10	@ clear bits 11 and 10 of FSR
 	tst	r3, #PSR_J_BIT			@ Java?
-	movne	pc, lr
+	bne	jazelle_abort
 	do_thumb_abort
 	ldreq	r3, [r2]			@ read aborted ARM instruction
 	do_ldrd_abort
@@ -32,4 +33,12 @@ ENTRY(v5tj_early_abort)
 	orreq	r1, r1, #1 << 11		@ yes.
 	mov	pc, lr
 
+jazelle_abort:
+	mov	r2, sp, lsr #13			@ get the top of the stack
+	mov	r2, r2, lsl #13			@ containing the thread_info structure
+	ldr	r3, [r2, #TI_JABORT_ADDR]	@ get the last Jazelle abort address
+	cmp	r0, r3				@ is it the same address
+	orreq	r1, r1, #1 << 11		@ mark it as a write
+	str	r0, [r2, #TI_JABORT_ADDR]	@ always store the last Jazelle abort
+	mov	pc, lr
 

include/asm-arm/thread_info.h

@@ -66,6 +66,7 @@ struct thread_info {
 	unsigned long		xenonstate;	/* Jazelle-X handler base register */
 #endif
 	struct restart_block	restart_block;
+	__u32			jabort_addr;
 };
 
 #define INIT_THREAD_INFO(tsk)						\