Commit e191043f authored by Catalin Marinas's avatar Catalin Marinas

ARMv7: Implement the architecture barriers

Starting with ARMv7, there are dedicated instruction for the ISB, DSB
and DMB barriers and there is no need to execute them as CP15
operations.
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent cfcb4c82
...@@ -156,7 +156,11 @@ extern unsigned int user_debug; ...@@ -156,7 +156,11 @@ extern unsigned int user_debug;
#define vectors_high() (0) #define vectors_high() (0)
#endif #endif
#if defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ >= 6 #if __LINUX_ARM_ARCH__ >= 7
#define isb() __asm__ __volatile__ ("isb" : : : "memory")
#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
: : "r" (0) : "memory") : : "r" (0) : "memory")
#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
......
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