ARM: OMAP: Add DSP common code

Add DSP common code for OMAP. This patch adds code to idle the
OMAP DSP.
Signed-off-by: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

arch/arm/plat-omap/Makefile

@@ -19,3 +19,7 @@ obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
 obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
+
+# DSP subsystem
+obj-y += dsp/
+obj-$(CONFIG_OMAP_DSP) += mailbox.o

arch/arm/plat-omap/dsp/Kconfig

+
+config OMAP_DSP
+	tristate "OMAP DSP driver (DSP Gateway)"
+	depends on ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP24XX
+	select OMAP_MMU_FWK
+	select OMAP_MBOX_FWK
+	help
+	  This enables OMAP DSP driver, DSP Gateway.
+
+config OMAP_DSP_MBCMD_VERBOSE
+	bool "Mailbox Command Verbose LOG"
+	depends on OMAP_DSP
+	help
+          This enables kernel log output in the Mailbox command exchanges
+	  in the DSP Gateway driver.
+
+config OMAP_DSP_TASK_MULTIOPEN
+	bool "DSP Task Multiopen Capability"
+	depends on OMAP_DSP
+	help
+          This enables DSP tasks to be opened by multiple times at a time.
+	  Otherwise, they can be opened only once at a time.
+
+config OMAP_DSP_FBEXPORT
+	bool "Framebuffer export to DSP"
+	depends on OMAP_DSP && FB
+	help
+          This enables to map the frame buffer to DSP.
+	  By doing this, DSP can access the frame buffer directly without
+	  bothering ARM.
+

arch/arm/plat-omap/dsp/Makefile

+#
+# Makefile for the OMAP DSP driver.
+#
+
+# The target object and module list name.
+
+obj-y := dsp_common.o
+
+obj-$(CONFIG_OMAP_DSP) += dsp.o
+
+# Declare multi-part drivers
+
+dsp-objs	:= dsp_core.o ipbuf.o mblog.o task.o \
+		   dsp_ctl_core.o dsp_ctl.o taskwatch.o error.o dsp_mem.o \
+		   uaccess_dsp.o

arch/arm/plat-omap/dsp/dsp_common.h

+/*
+ * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
+ *
+ * Copyright (C) 2002-2006 Nokia Corporation. All rights reserved.
+ *
+ * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef DRIVER_DSP_COMMON_H
+#define DRIVER_DSP_COMMON_H
+
+#include <linux/clk.h>
+#include <asm/arch/mmu.h>
+#include "hardware_dsp.h"
+
+#define DSPSPACE_SIZE	0x1000000
+
+#define omap_set_bit_regw(b,r) \
+	do { omap_writew(omap_readw(r) | (b), (r)); } while(0)
+#define omap_clr_bit_regw(b,r) \
+	do { omap_writew(omap_readw(r) & ~(b), (r)); } while(0)
+#define omap_set_bit_regl(b,r) \
+	do { omap_writel(omap_readl(r) | (b), (r)); } while(0)
+#define omap_clr_bit_regl(b,r) \
+	do { omap_writel(omap_readl(r) & ~(b), (r)); } while(0)
+#define omap_set_bits_regl(val,mask,r) \
+	do { omap_writel((omap_readl(r) & ~(mask)) | (val), (r)); } while(0)
+
+#define dspword_to_virt(dw)	((void *)(dspmem_base + ((dw) << 1)))
+#define dspbyte_to_virt(db)	((void *)(dspmem_base + (db)))
+#define virt_to_dspword(va) \
+	((dsp_long_t)(((unsigned long)(va) - dspmem_base) >> 1))
+#define virt_to_dspbyte(va) \
+	((dsp_long_t)((unsigned long)(va) - dspmem_base))
+#define is_dsp_internal_mem(va) \
+	(((unsigned long)(va) >= dspmem_base) &&  \
+	 ((unsigned long)(va) < dspmem_base + dspmem_size))
+#define is_dspbyte_internal_mem(db)	((db) < dspmem_size)
+#define is_dspword_internal_mem(dw)	(((dw) << 1) < dspmem_size)
+
+#ifdef CONFIG_ARCH_OMAP1
+/*
+ * MPUI byteswap/wordswap on/off
+ *   default setting: wordswap = all, byteswap = APIMEM only
+ */
+#define mpui_wordswap_on() \
+	omap_set_bits_regl(MPUI_CTRL_WORDSWAP_ALL, MPUI_CTRL_WORDSWAP_MASK, \
+			   MPUI_CTRL)
+
+#define mpui_wordswap_off() \
+	omap_set_bits_regl(MPUI_CTRL_WORDSWAP_NONE, MPUI_CTRL_WORDSWAP_MASK, \
+			   MPUI_CTRL)
+
+#define mpui_byteswap_on() \
+	omap_set_bits_regl(MPUI_CTRL_BYTESWAP_API, MPUI_CTRL_BYTESWAP_MASK, \
+			   MPUI_CTRL)
+
+#define mpui_byteswap_off() \
+	omap_set_bits_regl(MPUI_CTRL_BYTESWAP_NONE, MPUI_CTRL_BYTESWAP_MASK, \
+			   MPUI_CTRL)
+
+/*
+ * TC wordswap on / off
+ */
+#define tc_wordswap() \
+	do { \
+		omap_writel(TC_ENDIANISM_SWAP_WORD | TC_ENDIANISM_EN, \
+			    TC_ENDIANISM); \
+	} while(0)
+
+#define tc_noswap()	omap_clr_bit_regl(TC_ENDIANISM_EN, TC_ENDIANISM)
+
+/*
+ * enable priority registers, EMIF, MPUI control logic
+ */
+#define __dsp_enable()	omap_set_bit_regw(ARM_RSTCT1_DSP_RST, ARM_RSTCT1)
+#define __dsp_disable()	omap_clr_bit_regw(ARM_RSTCT1_DSP_RST, ARM_RSTCT1)
+#define __dsp_run()	omap_set_bit_regw(ARM_RSTCT1_DSP_EN, ARM_RSTCT1)
+#define __dsp_reset()	omap_clr_bit_regw(ARM_RSTCT1_DSP_EN, ARM_RSTCT1)
+#endif /* CONFIG_ARCH_OMAP1 */
+
+#ifdef CONFIG_ARCH_OMAP2
+/*
+ * PRCM / IPI control logic
+ */
+#define RSTCTRL_RST1_DSP	0x00000001
+#define RSTCTRL_RST2_DSP	0x00000002
+#define __dsp_core_enable() \
+	do { RM_RSTCTRL_DSP &= ~RSTCTRL_RST1_DSP; } while (0)
+#define __dsp_core_disable() \
+	do { RM_RSTCTRL_DSP |= RSTCTRL_RST1_DSP; } while (0)
+#define __dsp_per_enable() \
+	do { RM_RSTCTRL_DSP &= ~RSTCTRL_RST2_DSP; } while (0)
+#define __dsp_per_disable() \
+	do { RM_RSTCTRL_DSP |= RSTCTRL_RST2_DSP; } while (0)
+#endif /* CONFIG_ARCH_OMAP2 */
+
+typedef u32 dsp_long_t;	/* must have ability to carry TADD_ABORTADR */
+
+#if defined(CONFIG_ARCH_OMAP1)
+extern struct clk *dsp_ck_handle;
+extern struct clk *api_ck_handle;
+#elif defined(CONFIG_ARCH_OMAP2)
+extern struct clk *dsp_fck_handle;
+extern struct clk *dsp_ick_handle;
+#endif
+extern dsp_long_t dspmem_base, dspmem_size,
+		  daram_base, daram_size,
+		  saram_base, saram_size;
+
+enum cpustat_e {
+	CPUSTAT_RESET = 0,
+#ifdef CONFIG_ARCH_OMAP1
+	CPUSTAT_GBL_IDLE,
+	CPUSTAT_CPU_IDLE,
+#endif
+	CPUSTAT_RUN,
+	CPUSTAT_MAX
+};
+
+int dsp_set_rstvect(dsp_long_t adr);
+dsp_long_t dsp_get_rstvect(void);
+void dsp_set_idle_boot_base(dsp_long_t adr, size_t size);
+void dsp_reset_idle_boot_base(void);
+void dsp_cpustat_request(enum cpustat_e req);
+enum cpustat_e dsp_cpustat_get_stat(void);
+u16 dsp_cpustat_get_icrmask(void);
+void dsp_cpustat_set_icrmask(u16 mask);
+void dsp_register_mem_cb(int (*req_cb)(void), void (*rel_cb)(void));
+void dsp_unregister_mem_cb(void);
+
+#if defined(CONFIG_ARCH_OMAP1)
+static inline void dsp_clk_enable(void) {}
+static inline void dsp_clk_disable(void) {}
+#elif defined(CONFIG_ARCH_OMAP2)
+static inline void dsp_clk_enable(void)
+{
+	/*XXX should be handled in mach-omap[1,2] XXX*/
+	PM_PWSTCTRL_DSP = (1 << 18) | (1 << 0);
+	CM_AUTOIDLE_DSP |= (1 << 1);
+	CM_CLKSTCTRL_DSP |= (1 << 0);
+
+	clk_enable(dsp_fck_handle);
+	clk_enable(dsp_ick_handle);
+	__dsp_per_enable();
+}
+static inline void dsp_clk_disable(void)
+{
+	__dsp_per_disable();
+	clk_disable(dsp_ick_handle);
+	clk_disable(dsp_fck_handle);
+
+	PM_PWSTCTRL_DSP = (1 << 18) | (3 << 0);
+}
+#endif
+
+struct dsp_kfunc_device {
+	char		*name;
+	struct clk	*fck;
+	struct clk	*ick;;
+	spinlock_t	 lock;
+	int		 enabled;
+	int		 type;
+#define DSP_KFUNC_DEV_TYPE_COMMON	1
+#define DSP_KFUNC_DEV_TYPE_AUDIO	2
+
+	struct list_head	entry;
+
+	int	(*probe)(struct dsp_kfunc_device *, int);
+	int	(*remove)(struct dsp_kfunc_device *, int);
+	int	(*enable)(struct dsp_kfunc_device *, int);
+	int	(*disable)(struct dsp_kfunc_device *, int);
+};
+
+extern int dsp_kfunc_device_register(struct dsp_kfunc_device *);
+
+struct dsp_platform_data {
+	struct list_head kdev_list;
+};
+
+struct omap_dsp {
+	struct mutex		lock;
+	int			enabled;	/* stored peripheral status */
+	struct omap_mmu		*mmu;
+	struct omap_mbox	*mbox;
+	struct device		*dev;
+	struct list_head	*kdev_list;
+	int			initialized;
+};
+
+#if defined(CONFIG_ARCH_OMAP1)
+#define command_dvfs_stop(m) (0)
+#define command_dvfs_start(m) (0)
+#elif defined(CONFIG_ARCH_OMAP2)
+#define command_dvfs_stop(m) \
+	(((m)->cmd_l == KFUNC_POWER) && ((m)->data == DVFS_STOP))
+#define command_dvfs_start(m) \
+	(((m)->cmd_l == KFUNC_POWER) && ((m)->data == DVFS_START))
+#endif
+
+extern struct omap_dsp *omap_dsp;
+
+extern int dsp_late_init(void);
+
+#endif /* DRIVER_DSP_COMMON_H */

arch/arm/plat-omap/dsp/hardware_dsp.h

+/*
+ * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
+ *
+ * Copyright (C) 2002-2006 Nokia Corporation. All rights reserved.
+ *
+ * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __OMAP_DSP_HARDWARE_DSP_H
+#define __OMAP_DSP_HARDWARE_DSP_H
+
+#ifdef CONFIG_ARCH_OMAP1
+#include "omap1_dsp.h"
+#endif
+#ifdef CONFIG_ARCH_OMAP2
+#include "omap2_dsp.h"
+#endif
+
+#endif /* __OMAP_DSP_HARDWARE_DSP_H */

arch/arm/plat-omap/dsp/omap1_dsp.h

+/*
+ * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
+ *
+ * Copyright (C) 2002-2006 Nokia Corporation. All rights reserved.
+ *
+ * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __OMAP_DSP_OMAP1_DSP_H
+#define __OMAP_DSP_OMAP1_DSP_H
+
+#ifdef CONFIG_ARCH_OMAP15XX
+#define OMAP1510_DARAM_BASE	(OMAP1510_DSP_BASE + 0x0)
+#define OMAP1510_DARAM_SIZE	0x10000
+#define OMAP1510_SARAM_BASE	(OMAP1510_DSP_BASE + 0x10000)
+#define OMAP1510_SARAM_SIZE	0x18000
+#endif
+
+#ifdef CONFIG_ARCH_OMAP16XX
+#define OMAP16XX_DARAM_BASE	(OMAP16XX_DSP_BASE + 0x0)
+#define OMAP16XX_DARAM_SIZE	0x10000
+#define OMAP16XX_SARAM_BASE	(OMAP16XX_DSP_BASE + 0x10000)
+#define OMAP16XX_SARAM_SIZE	0x18000
+#endif
+
+/*
+ * Reset Control
+ */
+#define ARM_RSTCT1_SW_RST		0x0008
+#define ARM_RSTCT1_DSP_RST		0x0004
+#define ARM_RSTCT1_DSP_EN		0x0002
+#define ARM_RSTCT1_ARM_RST		0x0001
+
+/*
+ * MPUI
+ */
+#define MPUI_CTRL_WORDSWAP_MASK		0x00600000
+#define MPUI_CTRL_WORDSWAP_ALL		0x00000000
+#define MPUI_CTRL_WORDSWAP_NONAPI	0x00200000
+#define MPUI_CTRL_WORDSWAP_API		0x00400000
+#define MPUI_CTRL_WORDSWAP_NONE		0x00600000
+#define MPUI_CTRL_AP_MASK		0x001c0000
+#define MPUI_CTRL_AP_MDH		0x00000000
+#define MPUI_CTRL_AP_MHD		0x00040000
+#define MPUI_CTRL_AP_DMH		0x00080000
+#define MPUI_CTRL_AP_HMD		0x000c0000
+#define MPUI_CTRL_AP_DHM		0x00100000
+#define MPUI_CTRL_AP_HDM		0x00140000
+#define MPUI_CTRL_BYTESWAP_MASK		0x00030000
+#define MPUI_CTRL_BYTESWAP_NONE		0x00000000
+#define MPUI_CTRL_BYTESWAP_NONAPI	0x00010000
+#define MPUI_CTRL_BYTESWAP_ALL		0x00020000
+#define MPUI_CTRL_BYTESWAP_API		0x00030000
+#define MPUI_CTRL_TIMEOUT_MASK		0x0000ff00
+#define MPUI_CTRL_APIF_HNSTB_DIV_MASK	0x000000f0
+#define MPUI_CTRL_S_NABORT_GL		0x00000008
+#define MPUI_CTRL_S_NABORT_32BIT	0x00000004
+#define MPUI_CTRL_EN_TIMEOUT		0x00000002
+#define MPUI_CTRL_HF_MCUCLK		0x00000001
+#define DSP_BOOT_CONFIG_DIRECT		0x00000000
+#define DSP_BOOT_CONFIG_PSD_DIRECT	0x00000001
+#define DSP_BOOT_CONFIG_IDLE		0x00000002
+#define DSP_BOOT_CONFIG_DL16		0x00000003
+#define DSP_BOOT_CONFIG_DL32		0x00000004
+#define DSP_BOOT_CONFIG_MPUI		0x00000005
+#define DSP_BOOT_CONFIG_INTERNAL	0x00000006
+
+/*
+ * DSP boot mode
+ *   direct:        0xffff00
+ *   pseudo direct: 0x080000
+ *   MPUI:          branch 0x010000
+ *   internel:      branch 0x024000
+ */
+#define DSP_BOOT_ADR_DIRECT		0xffff00
+#define DSP_BOOT_ADR_PSD_DIRECT		0x080000
+#define DSP_BOOT_ADR_MPUI		0x010000
+#define DSP_BOOT_ADR_INTERNAL		0x024000
+
+/*
+ * TC
+ */
+#define TC_ENDIANISM_SWAP		0x00000002
+#define TC_ENDIANISM_SWAP_WORD		0x00000002
+#define TC_ENDIANISM_SWAP_BYTE		0x00000000
+#define TC_ENDIANISM_EN			0x00000001
+
+/*
+ * DSP MMU
+ */
+#define DSP_MMU_BASE			(0xfefed200)
+#define DSP_MMU_PREFETCH		(DSP_MMU_BASE + 0x00)
+#define DSP_MMU_WALKING_ST		(DSP_MMU_BASE + 0x04)
+#define DSP_MMU_CNTL			(DSP_MMU_BASE + 0x08)
+#define DSP_MMU_FAULT_AD_H		(DSP_MMU_BASE + 0x0c)
+#define DSP_MMU_FAULT_AD_L		(DSP_MMU_BASE + 0x10)
+#define DSP_MMU_FAULT_ST		(DSP_MMU_BASE + 0x14)
+#define DSP_MMU_IT_ACK			(DSP_MMU_BASE + 0x18)
+#define DSP_MMU_TTB_H			(DSP_MMU_BASE + 0x1c)
+#define DSP_MMU_TTB_L			(DSP_MMU_BASE + 0x20)
+#define DSP_MMU_LOCK			(DSP_MMU_BASE + 0x24)
+#define DSP_MMU_LD_TLB			(DSP_MMU_BASE + 0x28)
+#define DSP_MMU_CAM_H			(DSP_MMU_BASE + 0x2c)
+#define DSP_MMU_CAM_L			(DSP_MMU_BASE + 0x30)
+#define DSP_MMU_RAM_H			(DSP_MMU_BASE + 0x34)
+#define DSP_MMU_RAM_L			(DSP_MMU_BASE + 0x38)
+#define DSP_MMU_GFLUSH			(DSP_MMU_BASE + 0x3c)
+#define DSP_MMU_FLUSH_ENTRY		(DSP_MMU_BASE + 0x40)
+#define DSP_MMU_READ_CAM_H		(DSP_MMU_BASE + 0x44)
+#define DSP_MMU_READ_CAM_L		(DSP_MMU_BASE + 0x48)
+#define DSP_MMU_READ_RAM_H		(DSP_MMU_BASE + 0x4c)
+#define DSP_MMU_READ_RAM_L		(DSP_MMU_BASE + 0x50)
+
+#define DSP_MMU_CNTL_BURST_16MNGT_EN	0x0020
+#define DSP_MMU_CNTL_WTL_EN		0x0004
+#define DSP_MMU_CNTL_MMU_EN		0x0002
+#define DSP_MMU_CNTL_RESET_SW		0x0001
+
+#define DSP_MMU_FAULT_AD_H_DP		0x0100
+#define DSP_MMU_FAULT_AD_H_ADR_MASK	0x00ff
+
+#define DSP_MMU_FAULT_ST_PREF		0x0008
+#define DSP_MMU_FAULT_ST_PERM		0x0004
+#define DSP_MMU_FAULT_ST_TLB_MISS	0x0002
+#define DSP_MMU_FAULT_ST_TRANS		0x0001
+
+#define DSP_MMU_IT_ACK_IT_ACK		0x0001
+
+#define DSP_MMU_LOCK_BASE_MASK		0xfc00
+#define DSP_MMU_LOCK_BASE_SHIFT		10
+#define DSP_MMU_LOCK_VICTIM_MASK	0x03f0
+#define DSP_MMU_LOCK_VICTIM_SHIFT	4
+
+#define DSP_MMU_CAM_H_VA_TAG_H_MASK		0x0003
+
+#define DSP_MMU_CAM_L_VA_TAG_L1_MASK		0xc000
+#define DSP_MMU_CAM_L_VA_TAG_L2_MASK_1MB	0x0000
+#define DSP_MMU_CAM_L_VA_TAG_L2_MASK_64KB	0x3c00
+#define DSP_MMU_CAM_L_VA_TAG_L2_MASK_4KB	0x3fc0
+#define DSP_MMU_CAM_L_VA_TAG_L2_MASK_1KB	0x3ff0
+#define DSP_MMU_CAM_L_P				0x0008
+#define DSP_MMU_CAM_L_V				0x0004
+#define DSP_MMU_CAM_L_PAGESIZE_MASK		0x0003
+#define DSP_MMU_CAM_L_PAGESIZE_1MB		0x0000
+#define DSP_MMU_CAM_L_PAGESIZE_64KB		0x0001
+#define DSP_MMU_CAM_L_PAGESIZE_4KB		0x0002
+#define DSP_MMU_CAM_L_PAGESIZE_1KB		0x0003
+
+#define DSP_MMU_RAM_L_RAM_LSB_MASK	0xfc00
+#define DSP_MMU_RAM_L_AP_MASK		0x0300
+#define DSP_MMU_RAM_L_AP_NA		0x0000
+#define DSP_MMU_RAM_L_AP_RO		0x0200
+#define DSP_MMU_RAM_L_AP_FA		0x0300
+
+#define DSP_MMU_GFLUSH_GFLUSH		0x0001
+
+#define DSP_MMU_FLUSH_ENTRY_FLUSH_ENTRY	0x0001
+
+#define DSP_MMU_LD_TLB_RD		0x0002
+#define DSP_MMU_LD_TLB_LD		0x0001
+
+/*
+ * DSP ICR
+ */
+#define DSPREG_ICR_RESERVED_BITS	0xffc0
+#define DSPREG_ICR_EMIF			0x0020
+#define DSPREG_ICR_DPLL			0x0010
+#define DSPREG_ICR_PER			0x0008
+#define DSPREG_ICR_CACHE		0x0004
+#define DSPREG_ICR_DMA			0x0002
+#define DSPREG_ICR_CPU			0x0001
+
+#endif /* __OMAP_DSP_OMAP1_DSP_H */

arch/arm/plat-omap/dsp/omap2_dsp.h

+/*
+ * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
+ *
+ * Copyright (C) 2006 Nokia Corporation. All rights reserved.
+ *
+ * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __OMAP_DSP_OMAP2_DSP_H
+#define __OMAP_DSP_OMAP2_DSP_H
+
+#ifdef CONFIG_ARCH_OMAP24XX
+#define OMAP24XX_DARAM_BASE	(DSP_MEM_24XX_VIRT + 0x0)
+#define OMAP24XX_DARAM_SIZE	0x10000
+#define OMAP24XX_SARAM_BASE	(DSP_MEM_24XX_VIRT + 0x10000)
+#define OMAP24XX_SARAM_SIZE	0x18000
+#endif
+
+#include <asm/arch/hardware.h>
+#include "../../mach-omap2/prcm-regs.h"
+
+/*
+ * DSP IPI registers: mapped to 0xe1000000 -- use readX(), writeX()
+ */
+#define DSP_IPI_BASE			DSP_IPI_24XX_VIRT
+#define DSP_IPI_REVISION		(DSP_IPI_BASE + 0x00)
+#define DSP_IPI_SYSCONFIG		(DSP_IPI_BASE + 0x10)
+#define DSP_IPI_INDEX			(DSP_IPI_BASE + 0x40)
+#define DSP_IPI_ENTRY			(DSP_IPI_BASE + 0x44)
+#define DSP_IPI_ENABLE			(DSP_IPI_BASE + 0x48)
+#define DSP_IPI_IOMAP			(DSP_IPI_BASE + 0x4c)
+#define DSP_IPI_DSPBOOTCONFIG		(DSP_IPI_BASE + 0x50)
+
+#define DSP_IPI_ENTRY_ELMSIZEVALUE_MASK	0x00000003
+#define DSP_IPI_ENTRY_ELMSIZEVALUE_8	0x00000000
+#define DSP_IPI_ENTRY_ELMSIZEVALUE_16	0x00000001
+#define DSP_IPI_ENTRY_ELMSIZEVALUE_32	0x00000002
+
+#define DSP_BOOT_CONFIG_DIRECT		0x00000000
+#define DSP_BOOT_CONFIG_PSD_DIRECT	0x00000001
+#define DSP_BOOT_CONFIG_IDLE		0x00000002
+#define DSP_BOOT_CONFIG_DL16		0x00000003
+#define DSP_BOOT_CONFIG_DL32		0x00000004
+#define DSP_BOOT_CONFIG_API		0x00000005
+#define DSP_BOOT_CONFIG_INTERNAL	0x00000006
+
+/*
+ * DSP boot mode
+ *   direct:        0xffff00
+ *   pseudo direct: 0x080000
+ *   API:           branch 0x010000
+ *   internel:      branch 0x024000
+ */
+#define DSP_BOOT_ADR_DIRECT		0xffff00
+#define DSP_BOOT_ADR_PSD_DIRECT		0x080000
+#define DSP_BOOT_ADR_API		0x010000
+#define DSP_BOOT_ADR_INTERNAL		0x024000
+
+/*
+ * DSP MMU: mapped to 0xe2000000 -- use readX(), writeX()
+ */
+#define DSP_MMU_BASE			DSP_MMU_24XX_VIRT
+#define DSP_MMU_REVISION		(DSP_MMU_BASE + 0x00)
+#define DSP_MMU_SYSCONFIG		(DSP_MMU_BASE + 0x10)
+#define DSP_MMU_SYSSTATUS		(DSP_MMU_BASE + 0x14)
+#define DSP_MMU_IRQSTATUS		(DSP_MMU_BASE + 0x18)
+#define DSP_MMU_IRQENABLE		(DSP_MMU_BASE + 0x1c)
+#define DSP_MMU_WALKING_ST		(DSP_MMU_BASE + 0x40)
+#define DSP_MMU_CNTL			(DSP_MMU_BASE + 0x44)
+#define DSP_MMU_FAULT_AD		(DSP_MMU_BASE + 0x48)
+#define DSP_MMU_TTB			(DSP_MMU_BASE + 0x4c)
+#define DSP_MMU_LOCK			(DSP_MMU_BASE + 0x50)
+#define DSP_MMU_LD_TLB			(DSP_MMU_BASE + 0x54)
+#define DSP_MMU_CAM			(DSP_MMU_BASE + 0x58)
+#define DSP_MMU_RAM			(DSP_MMU_BASE + 0x5c)
+#define DSP_MMU_GFLUSH			(DSP_MMU_BASE + 0x60)
+#define DSP_MMU_FLUSH_ENTRY		(DSP_MMU_BASE + 0x64)
+#define DSP_MMU_READ_CAM		(DSP_MMU_BASE + 0x68)
+#define DSP_MMU_READ_RAM		(DSP_MMU_BASE + 0x6c)
+#define DSP_MMU_EMU_FAULT_AD		(DSP_MMU_BASE + 0x70)
+
+#define DSP_MMU_SYSCONFIG_CLOCKACTIVITY_MASK	0x00000300
+#define DSP_MMU_SYSCONFIG_IDLEMODE_MASK		0x00000018
+#define DSP_MMU_SYSCONFIG_SOFTRESET		0x00000002
+#define DSP_MMU_SYSCONFIG_AUTOIDLE		0x00000001
+
+#define DSP_MMU_IRQ_MULTIHITFAULT	0x00000010
+#define DSP_MMU_IRQ_TABLEWALKFAULT	0x00000008
+#define DSP_MMU_IRQ_EMUMISS		0x00000004
+#define DSP_MMU_IRQ_TRANSLATIONFAULT	0x00000002
+#define DSP_MMU_IRQ_TLBMISS		0x00000001
+
+#define DSP_MMU_CNTL_EMUTLBUPDATE	0x00000008
+#define DSP_MMU_CNTL_TWLENABLE		0x00000004
+#define DSP_MMU_CNTL_MMUENABLE		0x00000002
+
+#define DSP_MMU_LOCK_BASE_MASK		0x00007c00
+#define DSP_MMU_LOCK_BASE_SHIFT		10
+#define DSP_MMU_LOCK_VICTIM_MASK	0x000001f0
+#define DSP_MMU_LOCK_VICTIM_SHIFT	4
+
+#define DSP_MMU_CAM_VATAG_MASK		0xfffff000
+#define DSP_MMU_CAM_P			0x00000008
+#define DSP_MMU_CAM_V			0x00000004
+#define DSP_MMU_CAM_PAGESIZE_MASK	0x00000003
+#define DSP_MMU_CAM_PAGESIZE_1MB	0x00000000
+#define DSP_MMU_CAM_PAGESIZE_64KB	0x00000001
+#define DSP_MMU_CAM_PAGESIZE_4KB	0x00000002
+#define DSP_MMU_CAM_PAGESIZE_16MB	0x00000003
+
+#define DSP_MMU_RAM_PADDR_MASK		0xfffff000
+#define DSP_MMU_RAM_ENDIANNESS		0x00000200
+#define DSP_MMU_RAM_ENDIANNESS_BIG	0x00000200
+#define DSP_MMU_RAM_ENDIANNESS_LITTLE	0x00000000
+#define DSP_MMU_RAM_ELEMENTSIZE_MASK	0x00000180
+#define DSP_MMU_RAM_ELEMENTSIZE_8	0x00000000
+#define DSP_MMU_RAM_ELEMENTSIZE_16	0x00000080
+#define DSP_MMU_RAM_ELEMENTSIZE_32	0x00000100
+#define DSP_MMU_RAM_ELEMENTSIZE_NONE	0x00000180
+#define DSP_MMU_RAM_MIXED		0x00000040
+
+#define DSP_MMU_GFLUSH_GFLUSH		0x00000001
+
+#define DSP_MMU_FLUSH_ENTRY_FLUSH_ENTRY	0x00000001
+
+#define DSP_MMU_LD_TLB_LD		0x00000001
+
+/*
+ * DSP ICR
+ */
+#define DSPREG_ICR_RESERVED_BITS	0xfc00
+#define DSPREG_ICR_HWA			0x0200
+#define DSPREG_ICR_IPORT		0x0100
+#define DSPREG_ICR_MPORT		0x0080
+#define DSPREG_ICR_XPORT		0x0040
+#define DSPREG_ICR_DPORT		0x0020
+#define DSPREG_ICR_DPLL			0x0010
+#define DSPREG_ICR_PER			0x0008
+#define DSPREG_ICR_CACHE		0x0004
+#define DSPREG_ICR_DMA			0x0002
+#define DSPREG_ICR_CPU			0x0001
+
+#endif /* __OMAP_DSP_OMAP2_DSP_H */

arch/arm/plat-omap/mcbsp.c

@@ -197,6 +197,7 @@ static int omap_mcbsp_check(unsigned int id)
 static void omap_mcbsp_dsp_request(void)
 {
 	if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+		omap_dsp_request_mem();
 		clk_enable(mcbsp_dsp_ck);
 		clk_enable(mcbsp_api_ck);
 
@@ -215,6 +216,7 @@ static void omap_mcbsp_dsp_request(void)
 static void omap_mcbsp_dsp_free(void)
 {
 	if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+		omap_dsp_release_mem();
 		clk_disable(mcbsp_dspxor_ck);
 		clk_disable(mcbsp_dsp_ck);
 		clk_disable(mcbsp_api_ck);