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Commit ccaa36f7 authored by Linus Torvalds's avatar Linus Torvalds
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc 

* git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (29 commits)
  [POWERPC] Fix rheap alignment problem
  [POWERPC] Use check_legacy_ioport() for ISAPnP
  [POWERPC] Avoid NULL pointer in gpio1_interrupt
  [POWERPC] Enable generic rtc hook for the MPC8349 mITX
  [POWERPC] Add powerpc get/set_rtc_time interface to new generic rtc class
  [POWERPC] Create a "wrapper" script and use it in arch/powerpc/boot
  [POWERPC] fix spin lock nesting in hvc_iseries
  [POWERPC] EEH failure to mark pci slot as frozen.
  [POWERPC] update powerpc defconfig files after libata kconfig breakage
  [POWERPC] enable sysrq in pmac32_defconfig
  [POWERPC] UPIO_TSI cleanup
  [POWERPC] rewrite mkprep and mkbugboot in sane C
  [POWERPC] maple/pci iomem annotations
  [POWERPC] powerpc oprofile __user annotations
  [POWERPC] cell spufs iomem annotations
  [POWERPC] NULL noise removal: spufs
  [POWERPC] ppc math-emu needs -fno-builtin-fabs for math.c and fabs.c
  [POWERPC] update mpc8349_itx_defconfig and remove some debug settings
  [POWERPC] Always call cede in pseries dedicated idle loop
  [POWERPC] Fix loop logic in irq_alloc_virt()
  ...
parents b4a9071a 5e980823
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Showing with 3395 additions and 749 deletions
arch/powerpc/Makefile
View file @ ccaa36f7
......@@ -20,6 +20,7 @@ CROSS32_COMPILE ?=
CROSS32CC := $(CROSS32_COMPILE)gcc
CROSS32AS := $(CROSS32_COMPILE)as
CROSS32LD := $(CROSS32_COMPILE)ld
CROSS32AR := $(CROSS32_COMPILE)ar
CROSS32OBJCOPY := $(CROSS32_COMPILE)objcopy
ifeq ($(HAS_BIARCH),y)
......@@ -28,10 +29,11 @@ CROSS32CC := $(CC) -m32
CROSS32AS := $(AS) -a32
CROSS32LD := $(LD) -m elf32ppc
CROSS32OBJCOPY := $(OBJCOPY)
CROSS32AR := $(AR)
endif
endif
export CROSS32CC CROSS32AS CROSS32LD CROSS32OBJCOPY
export CROSS32CC CROSS32AS CROSS32LD CROSS32AR CROSS32OBJCOPY
KBUILD_DEFCONFIG := $(shell uname -m)_defconfig
......@@ -146,7 +148,7 @@ all: $(KBUILD_IMAGE)
CPPFLAGS_vmlinux.lds := -Upowerpc
BOOT_TARGETS = zImage zImage.initrd znetboot znetboot.initrd vmlinux.sm uImage vmlinux.bin
BOOT_TARGETS = zImage zImage.initrd uImage
PHONY += $(BOOT_TARGETS)
......
arch/powerpc/boot/Makefile
View file @ ccaa36f7
This diff is collapsed.
arch/powerpc/boot/dts/mpc8560ads.dts 0 → 100644
View file @ ccaa36f7
/*
* MPC8560 ADS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/ {
model = "MPC8560ADS";
compatible = "MPC85xxADS";
#address-cells = <1>;
#size-cells = <1>;
linux,phandle = <100>;
cpus {
#cpus = <1>;
#address-cells = <1>;
#size-cells = <0>;
linux,phandle = <200>;
PowerPC,8560@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <8000>; // L1, 32K
i-cache-size = <8000>; // L1, 32K
timebase-frequency = <04ead9a0>;
bus-frequency = <13ab6680>;
clock-frequency = <312c8040>;
32-bit;
linux,phandle = <201>;
linux,boot-cpu;
};
};
memory {
device_type = "memory";
linux,phandle = <300>;
reg = <00000000 10000000>;
};
soc8560@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
bus-frequency = <13ab6680>;
mdio@24520 {
device_type = "mdio";
compatible = "gianfar";
reg = <24520 20>;
linux,phandle = <24520>;
#address-cells = <1>;
#size-cells = <0>;
ethernet-phy@0 {
linux,phandle = <2452000>;
interrupt-parent = <40000>;
interrupts = <35 1>;
reg = <0>;
device_type = "ethernet-phy";
};
ethernet-phy@1 {
linux,phandle = <2452001>;
interrupt-parent = <40000>;
interrupts = <35 1>;
reg = <1>;
device_type = "ethernet-phy";
};
ethernet-phy@2 {
linux,phandle = <2452002>;
interrupt-parent = <40000>;
interrupts = <37 1>;
reg = <2>;
device_type = "ethernet-phy";
};
ethernet-phy@3 {
linux,phandle = <2452003>;
interrupt-parent = <40000>;
interrupts = <37 1>;
reg = <3>;
device_type = "ethernet-phy";
};
};
ethernet@24000 {
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <24000 1000>;
address = [ 00 00 0C 00 00 FD ];
interrupts = <d 2 e 2 12 2>;
interrupt-parent = <40000>;
phy-handle = <2452000>;
};
ethernet@25000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <25000 1000>;
address = [ 00 00 0C 00 01 FD ];
interrupts = <13 2 14 2 18 2>;
interrupt-parent = <40000>;
phy-handle = <2452001>;
};
pci@8000 {
linux,phandle = <8000>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "85xx";
device_type = "pci";
reg = <8000 400>;
clock-frequency = <3f940aa>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x2 */
1000 0 0 1 40000 31 1
1000 0 0 2 40000 32 1
1000 0 0 3 40000 33 1
1000 0 0 4 40000 34 1
/* IDSEL 0x3 */
1800 0 0 1 40000 34 1
1800 0 0 2 40000 31 1
1800 0 0 3 40000 32 1
1800 0 0 4 40000 33 1
/* IDSEL 0x4 */
2000 0 0 1 40000 33 1
2000 0 0 2 40000 34 1
2000 0 0 3 40000 31 1
2000 0 0 4 40000 32 1
/* IDSEL 0x5 */
2800 0 0 1 40000 32 1
2800 0 0 2 40000 33 1
2800 0 0 3 40000 34 1
2800 0 0 4 40000 31 1
/* IDSEL 12 */
6000 0 0 1 40000 31 1
6000 0 0 2 40000 32 1
6000 0 0 3 40000 33 1
6000 0 0 4 40000 34 1
/* IDSEL 13 */
6800 0 0 1 40000 34 1
6800 0 0 2 40000 31 1
6800 0 0 3 40000 32 1
6800 0 0 4 40000 33 1
/* IDSEL 14*/
7000 0 0 1 40000 33 1
7000 0 0 2 40000 34 1
7000 0 0 3 40000 31 1
7000 0 0 4 40000 32 1
/* IDSEL 15 */
7800 0 0 1 40000 32 1
7800 0 0 2 40000 33 1
7800 0 0 3 40000 34 1
7800 0 0 4 40000 31 1
/* IDSEL 18 */
9000 0 0 1 40000 31 1
9000 0 0 2 40000 32 1
9000 0 0 3 40000 33 1
9000 0 0 4 40000 34 1
/* IDSEL 19 */
9800 0 0 1 40000 34 1
9800 0 0 2 40000 31 1
9800 0 0 3 40000 32 1
9800 0 0 4 40000 33 1
/* IDSEL 20 */
a000 0 0 1 40000 33 1
a000 0 0 2 40000 34 1
a000 0 0 3 40000 31 1
a000 0 0 4 40000 32 1
/* IDSEL 21 */
a800 0 0 1 40000 32 1
a800 0 0 2 40000 33 1
a800 0 0 3 40000 34 1
a800 0 0 4 40000 31 1>;
interrupt-parent = <40000>;
interrupts = <42 0>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 01000000>;
};
pic@40000 {
linux,phandle = <40000>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <40000 20100>;
built-in;
device_type = "open-pic";
};
cpm@e0000000 {
linux,phandle = <e0000000>;
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM2";
ranges = <0 0 c0000>;
reg = <80000 40000>;
command-proc = <919c0>;
brg-frequency = <9d5b340>;
pic@90c00 {
linux,phandle = <90c00>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <1e 0>;
interrupt-parent = <40000>;
reg = <90c00 80>;
built-in;
device_type = "cpm-pic";
};
scc@91a00 {
device_type = "serial";
compatible = "cpm_uart";
model = "SCC";
device-id = <1>;
reg = <91a00 20 88000 100>;
clock-setup = <00ffffff 0>;
rx-clock = <1>;
tx-clock = <1>;
current-speed = <1c200>;
interrupts = <64 1>;
interrupt-parent = <90c00>;
};
scc@91a20 {
device_type = "serial";
compatible = "cpm_uart";
model = "SCC";
device-id = <2>;
reg = <91a20 20 88100 100>;
clock-setup = <ff00ffff 90000>;
rx-clock = <2>;
tx-clock = <2>;
current-speed = <1c200>;
interrupts = <65 1>;
interrupt-parent = <90c00>;
};
fcc@91320 {
device_type = "network";
compatible = "fs_enet";
model = "FCC";
device-id = <2>;
reg = <91320 20 88500 100 913a0 30>;
mac-address = [ 00 00 0C 00 02 FD ];
clock-setup = <ff00ffff 250000>;
rx-clock = <15>;
tx-clock = <16>;
interrupts = <5d 1>;
interrupt-parent = <90c00>;
phy-handle = <2452002>;
};
fcc@91340 {
device_type = "network";
compatible = "fs_enet";
model = "FCC";
device-id = <3>;
reg = <91340 20 88600 100 913d0 30>;
mac-address = [ 00 00 0C 00 03 FD ];
clock-setup = <ffff00ff 3700>;
rx-clock = <17>;
tx-clock = <18>;
interrupts = <5e 1>;
interrupt-parent = <90c00>;
phy-handle = <2452003>;
};
};
};
};
arch/powerpc/boot/wrapper 0 → 100755
View file @ ccaa36f7
#!/bin/sh
# Copyright (C) 2006 Paul Mackerras, IBM Corporation <paulus@samba.org>
# This program may be used under the terms of version 2 of the GNU
# General Public License.
# This script takes a kernel binary and optionally an initrd image
# and/or a device-tree blob, and creates a bootable zImage for a
# given platform.
# Options:
# -o zImage specify output file
# -p platform specify platform (links in $platform.o)
# -i initrd specify initrd file
# -d devtree specify device-tree blob
# -s tree.dts specify device-tree source file (needs dtc installed)
# -c cache $kernel.strip.gz (use if present & newer, else make)
# -C prefix specify command prefix for cross-building tools
# (strip, objcopy, ld)
# -D dir specify directory containing data files used by script
# (default ./arch/powerpc/boot)
# -W dir specify working directory for temporary files (default .)
# defaults
kernel=
ofile=zImage
platform=of
initrd=
dtb=
dts=
cacheit=
# cross-compilation prefix
CROSS=
# directory for object and other files used by this script
object=arch/powerpc/boot
# directory for working files
tmpdir=.
usage() {
echo 'Usage: wrapper [-o output] [-p platform] [-i initrd]' >&2
echo ' [-d devtree] [-s tree.dts] [-c] [-C cross-prefix]' >&2
echo ' [-D datadir] [-W workingdir] [vmlinux]' >&2
exit 1
}
while [ "$#" -gt 0 ]; do
case "$1" in
-o)
shift
[ "$#" -gt 0 ] || usage
ofile="$1"
;;
-p)
shift
[ "$#" -gt 0 ] || usage
platform="$1"
;;
-i)
shift
[ "$#" -gt 0 ] || usage
initrd="$1"
;;
-d)
shift
[ "$#" -gt 0 ] || usage
dtb="$1"
;;
-s)
shift
[ "$#" -gt 0 ] || usage
dts="$1"
;;
-c)
cacheit=y
;;
-C)
shift
[ "$#" -gt 0 ] || usage
CROSS="$1"
;;
-D)
shift
[ "$#" -gt 0 ] || usage
object="$1"
;;
-W)
shift
[ "$#" -gt 0 ] || usage
tmpdir="$1"
;;
-?)
usage
;;
*)
[ -z "$kernel" ] || usage
kernel="$1"
;;
esac
shift
done
if [ -n "$dts" ]; then
if [ -z "$dtb" ]; then
dtb="$platform.dtb"
fi
dtc -O dtb -o "$dtb" -b 0 -V 16 "$dts" || exit 1
fi
if [ -z "$kernel" ]; then
kernel=vmlinux
fi
platformo=$object/"$platform".o
lds=$object/zImage.lds
ext=strip
objflags=-S
tmp=$tmpdir/zImage.$$.o
ksection=.kernel:vmlinux.strip
isection=.kernel:initrd
case "$platform" in
pmac|pseries|chrp)
platformo=$object/of.o
;;
pmaccoff)
platformo=$object/of.o
lds=$object/zImage.coff.lds
;;
miboot|uboot)
# miboot and U-boot want just the bare bits, not an ELF binary
ext=bin
objflags="-O binary"
tmp="$ofile"
ksection=image
isection=initrd
;;
esac
vmz="$tmpdir/`basename \"$kernel\"`.$ext"
if [ -z "$cacheit" -o ! -f "$vmz.gz" -o "$vmz.gz" -ot "$kernel" ]; then
${CROSS}objcopy $objflags "$kernel" "$vmz.$$"
gzip -f -9 "$vmz.$$"
if [ -n "$cacheit" ]; then
mv -f "$vmz.$$.gz" "$vmz.gz"
else
vmz="$vmz.$$"
fi
fi
case "$platform" in
uboot)
rm -f "$ofile"
version=`${CROSS}strings "$kernel" | grep '^Linux version [-0-9.]' | \
cut -d' ' -f3`
if [ -n "$version" ]; then
version="-n Linux-$version"
fi
mkimage -A ppc -O linux -T kernel -C gzip -a 00000000 -e 00000000 \
$version -d "$vmz.gz" "$ofile"
if [ -z "$cacheit" ]; then
rm -f $vmz.gz
fi
exit 0
;;
esac
addsec() {
${CROSS}objcopy $4 $1 \
--add-section=$3="$2" \
--set-section-flags=$3=contents,alloc,load,readonly,data
}
addsec $tmp "$vmz.gz" $ksection $object/empty.o
if [ -z "$cacheit" ]; then
rm -f "$vmz.gz"
fi
if [ -n "$initrd" ]; then
addsec $tmp "$initrd" initrd
fi
if [ -n "$dtb" ]; then
addsec $tmp "$dtb" dtb
fi
if [ "$platform" != "miboot" ]; then
${CROSS}ld -m elf32ppc -T $lds -o "$ofile" \
$object/crt0.o $platformo $tmp $object/wrapper.a
rm $tmp
fi
# post-processing needed for some platforms
case "$platform" in
pseries|chrp)
$object/addnote "$ofile"
;;
pmaccoff)
${CROSS}objcopy -O aixcoff-rs6000 --set-start 0x500000 "$ofile"
$object/hack-coff "$ofile"
;;
esac
arch/powerpc/configs/chrp32_defconfig
View file @ ccaa36f7
......@@ -492,7 +492,7 @@ CONFIG_SCSI_SPI_ATTRS=y
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_SATA is not set
# CONFIG_ATA is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
......
arch/powerpc/configs/g5_defconfig
View file @ ccaa36f7
......@@ -490,23 +490,23 @@ CONFIG_SCSI_SPI_ATTRS=y
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
CONFIG_SCSI_SATA=y
# CONFIG_SCSI_SATA_AHCI is not set
CONFIG_SCSI_SATA_SVW=y
CONFIG_ATA=y
# CONFIG_SATA_AHCI is not set
CONFIG_SATA_SVW=y
# CONFIG_SCSI_ATA_PIIX is not set
# CONFIG_SCSI_SATA_MV is not set
# CONFIG_SCSI_SATA_NV is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_SCSI_PDC_ADMA is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_SATA_QSTOR is not set
# CONFIG_SCSI_SATA_PROMISE is not set
# CONFIG_SCSI_SATA_SX4 is not set
# CONFIG_SCSI_SATA_SIL is not set
# CONFIG_SCSI_SATA_SIL24 is not set
# CONFIG_SCSI_SATA_SIS is not set
# CONFIG_SCSI_SATA_ULI is not set
# CONFIG_SCSI_SATA_VIA is not set
# CONFIG_SCSI_SATA_VITESSE is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SX4 is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIL24 is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_EATA is not set
......
arch/powerpc/configs/iseries_defconfig
View file @ ccaa36f7
......@@ -475,7 +475,7 @@ CONFIG_SCSI_FC_ATTRS=y
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_SATA is not set
# CONFIG_ATA is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
......
arch/powerpc/configs/mpc7448_hpc2_defconfig
View file @ ccaa36f7
......@@ -413,23 +413,23 @@ CONFIG_BLK_DEV_SD=y
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
CONFIG_SCSI_SATA=y
# CONFIG_SCSI_SATA_AHCI is not set
# CONFIG_SCSI_SATA_SVW is not set
CONFIG_ATA=y
# CONFIG_SATA_AHCI is not set
# CONFIG_SATA_SVW is not set
# CONFIG_SCSI_ATA_PIIX is not set
CONFIG_SCSI_SATA_MV=y
# CONFIG_SCSI_SATA_NV is not set
CONFIG_SATA_MV=y
# CONFIG_SATA_NV is not set
# CONFIG_SCSI_PDC_ADMA is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_SATA_QSTOR is not set
# CONFIG_SCSI_SATA_PROMISE is not set
# CONFIG_SCSI_SATA_SX4 is not set
# CONFIG_SCSI_SATA_SIL is not set
# CONFIG_SCSI_SATA_SIL24 is not set
# CONFIG_SCSI_SATA_SIS is not set
# CONFIG_SCSI_SATA_ULI is not set
# CONFIG_SCSI_SATA_VIA is not set
# CONFIG_SCSI_SATA_VITESSE is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SX4 is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIL24 is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_EATA is not set
......
arch/powerpc/configs/mpc834x_itx_defconfig
View file @ ccaa36f7
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.18-rc6
# Sun Sep 10 10:28:05 2006
# Linux kernel version: 2.6.18
# Mon Sep 25 19:41:14 2006
#
# CONFIG_PPC64 is not set
CONFIG_PPC32=y
......@@ -21,6 +21,7 @@ CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_PPC_OF=y
CONFIG_PPC_UDBG_16550=y
# CONFIG_GENERIC_TBSYNC is not set
CONFIG_AUDIT_ARCH=y
CONFIG_DEFAULT_UIMAGE=y
#
......@@ -61,25 +62,25 @@ CONFIG_SYSVIPC=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
# CONFIG_RELAY is not set
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_EMBEDDED=y
CONFIG_SYSCTL=y
# CONFIG_KALLSYMS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_RT_MUTEXES=y
CONFIG_FUTEX=y
# CONFIG_EPOLL is not set
CONFIG_SHMEM=y
CONFIG_SLAB=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
......@@ -259,7 +260,6 @@ CONFIG_TCP_CONG_BIC=y
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
......@@ -313,6 +313,7 @@ CONFIG_MTD_CHAR=y
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
#
# RAM/ROM/Flash chip drivers
......@@ -464,23 +465,23 @@ CONFIG_SCSI_SPI_ATTRS=y
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
CONFIG_SCSI_SATA=y
# CONFIG_SCSI_SATA_AHCI is not set
# CONFIG_SCSI_SATA_SVW is not set
CONFIG_ATA=y
# CONFIG_SATA_AHCI is not set
# CONFIG_SATA_SVW is not set
# CONFIG_SCSI_ATA_PIIX is not set
# CONFIG_SCSI_SATA_MV is not set
# CONFIG_SCSI_SATA_NV is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_SCSI_PDC_ADMA is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_SATA_QSTOR is not set
# CONFIG_SCSI_SATA_PROMISE is not set
# CONFIG_SCSI_SATA_SX4 is not set
CONFIG_SCSI_SATA_SIL=y
# CONFIG_SCSI_SATA_SIL24 is not set
# CONFIG_SCSI_SATA_SIS is not set
# CONFIG_SCSI_SATA_ULI is not set
# CONFIG_SCSI_SATA_VIA is not set
# CONFIG_SCSI_SATA_VITESSE is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SX4 is not set
CONFIG_SATA_SIL=y
# CONFIG_SATA_SIL24 is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_EATA is not set
......@@ -1277,11 +1278,11 @@ CONFIG_PLIST=y
#
# Kernel hacking
#
CONFIG_PRINTK_TIME=y
# CONFIG_PRINTK_TIME is not set
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_LOG_BUF_SHIFT=17
CONFIG_LOG_BUF_SHIFT=14
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_DEBUG_SLAB is not set
......@@ -1293,15 +1294,15 @@ CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_DEBUG_VM is not set
CONFIG_FORCED_INLINING=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_DEBUGGER is not set
# CONFIG_BDI_SWITCH is not set
CONFIG_BOOTX_TEXT=y
CONFIG_SERIAL_TEXT_DEBUG=y
# CONFIG_BOOTX_TEXT is not set
# CONFIG_SERIAL_TEXT_DEBUG is not set
# CONFIG_PPC_EARLY_DEBUG is not set
#
......@@ -1314,6 +1315,8 @@ CONFIG_SERIAL_TEXT_DEBUG=y
# Cryptographic options
#
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y
# CONFIG_CRYPTO_MANAGER is not set
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_MD4 is not set
......@@ -1323,6 +1326,8 @@ CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_CBC is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
......
arch/powerpc/configs/mpc8560_ads_defconfig 0 → 100644
View file @ ccaa36f7
This diff is collapsed.
arch/powerpc/configs/pmac32_defconfig
View file @ ccaa36f7
......@@ -682,7 +682,7 @@ CONFIG_SCSI_AIC7XXX_OLD=m
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_SATA is not set
# CONFIG_ATA is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
......@@ -1826,7 +1826,7 @@ CONFIG_OPROFILE=y
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
# CONFIG_MAGIC_SYSRQ is not set
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_LOG_BUF_SHIFT=14
......
arch/powerpc/configs/ppc64_defconfig
View file @ ccaa36f7
......@@ -520,23 +520,23 @@ CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
CONFIG_SCSI_SATA=y
# CONFIG_SCSI_SATA_AHCI is not set
CONFIG_SCSI_SATA_SVW=y
CONFIG_ATA=y
# CONFIG_SATA_AHCI is not set
CONFIG_SATA_SVW=y
# CONFIG_SCSI_ATA_PIIX is not set
# CONFIG_SCSI_SATA_MV is not set
# CONFIG_SCSI_SATA_NV is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_SCSI_PDC_ADMA is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_SATA_QSTOR is not set
# CONFIG_SCSI_SATA_PROMISE is not set
# CONFIG_SCSI_SATA_SX4 is not set
# CONFIG_SCSI_SATA_SIL is not set
# CONFIG_SCSI_SATA_SIL24 is not set
# CONFIG_SCSI_SATA_SIS is not set
# CONFIG_SCSI_SATA_ULI is not set
# CONFIG_SCSI_SATA_VIA is not set
# CONFIG_SCSI_SATA_VITESSE is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SX4 is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIL24 is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_EATA is not set
......
arch/powerpc/configs/pseries_defconfig
View file @ ccaa36f7
......@@ -506,7 +506,7 @@ CONFIG_SCSI_SAS_ATTRS=m
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_SATA is not set
# CONFIG_ATA is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
......
arch/powerpc/kernel/irq.c
View file @ ccaa36f7
......@@ -777,7 +777,6 @@ unsigned int irq_alloc_virt(struct irq_host *host,
{
unsigned long flags;
unsigned int i, j, found = NO_IRQ;
unsigned int limit = irq_virq_count - count;
if (count == 0 || count > (irq_virq_count - NUM_ISA_INTERRUPTS))
return NO_IRQ;
......@@ -794,14 +793,16 @@ unsigned int irq_alloc_virt(struct irq_host *host,
/* Look for count consecutive numbers in the allocatable
* (non-legacy) space
*/
for (i = NUM_ISA_INTERRUPTS; i <= limit; ) {
for (j = i; j < (i + count); j++)
if (irq_map[j].host != NULL) {
i = j + 1;
continue;
}
found = i;
break;
for (i = NUM_ISA_INTERRUPTS, j = 0; i < irq_virq_count; i++) {
if (irq_map[i].host != NULL)
j = 0;
else
j++;
if (j == count) {
found = i - count + 1;
break;
}
}
if (found == NO_IRQ) {
spin_unlock_irqrestore(&irq_big_lock, flags);
......
arch/powerpc/kernel/ptrace.c
View file @ ccaa36f7
......@@ -526,9 +526,7 @@ static void do_syscall_trace(void)
void do_syscall_trace_enter(struct pt_regs *regs)
{
#ifdef CONFIG_PPC64
secure_computing(regs->gpr[0]);
#endif
if (test_thread_flag(TIF_SYSCALL_TRACE)
&& (current->ptrace & PT_PTRACED))
......@@ -548,12 +546,8 @@ void do_syscall_trace_enter(struct pt_regs *regs)
void do_syscall_trace_leave(struct pt_regs *regs)
{
#ifdef CONFIG_PPC32
secure_computing(regs->gpr[0]);
#endif
if (unlikely(current->audit_context))
audit_syscall_exit((regs->ccr&0x1000)?AUDITSC_FAILURE:AUDITSC_SUCCESS,
audit_syscall_exit((regs->ccr&0x10000000)?AUDITSC_FAILURE:AUDITSC_SUCCESS,
regs->result);
if ((test_thread_flag(TIF_SYSCALL_TRACE)
......@@ -561,8 +555,3 @@ void do_syscall_trace_leave(struct pt_regs *regs)
&& (current->ptrace & PT_PTRACED))
do_syscall_trace();
}
#ifdef CONFIG_PPC32
EXPORT_SYMBOL(do_syscall_trace_enter);
EXPORT_SYMBOL(do_syscall_trace_leave);
#endif
arch/powerpc/kernel/sysfs.c
View file @ ccaa36f7
......@@ -25,8 +25,8 @@ static DEFINE_PER_CPU(struct cpu, cpu_devices);
/* SMT stuff */
#ifdef CONFIG_PPC_MULTIPLATFORM
/* default to snooze disabled */
DEFINE_PER_CPU(unsigned long, smt_snooze_delay);
/* Time in microseconds we delay before sleeping in the idle loop */
DEFINE_PER_CPU(unsigned long, smt_snooze_delay) = { 100 };
static ssize_t store_smt_snooze_delay(struct sys_device *dev, const char *buf,
size_t count)
......
arch/powerpc/kernel/time.c
View file @ ccaa36f7
......@@ -1041,6 +1041,48 @@ void __init time_init(void)
set_dec(tb_ticks_per_jiffy);
}
#ifdef CONFIG_RTC_CLASS
static int set_rtc_class_time(struct rtc_time *tm)
{
int err;
struct class_device *class_dev =
rtc_class_open(CONFIG_RTC_HCTOSYS_DEVICE);
if (class_dev == NULL)
return -ENODEV;
err = rtc_set_time(class_dev, tm);
rtc_class_close(class_dev);
return 0;
}
static void get_rtc_class_time(struct rtc_time *tm)
{
int err;
struct class_device *class_dev =
rtc_class_open(CONFIG_RTC_HCTOSYS_DEVICE);
if (class_dev == NULL)
return;
err = rtc_read_time(class_dev, tm);
rtc_class_close(class_dev);
return;
}
int __init rtc_class_hookup(void)
{
ppc_md.get_rtc_time = get_rtc_class_time;
ppc_md.set_rtc_time = set_rtc_class_time;
return 0;
}
#endif /* CONFIG_RTC_CLASS */
#define FEBRUARY 2
#define STARTOFTIME 1970
......
arch/powerpc/lib/Makefile
View file @ ccaa36f7
......@@ -14,9 +14,15 @@ endif
obj-$(CONFIG_PPC64) += checksum_64.o copypage_64.o copyuser_64.o \
memcpy_64.o usercopy_64.o mem_64.o string.o \
strcase.o
obj-$(CONFIG_QUICC_ENGINE) += rheap.o
obj-$(CONFIG_XMON) += sstep.o
ifeq ($(CONFIG_PPC64),y)
obj-$(CONFIG_SMP) += locks.o
obj-$(CONFIG_DEBUG_KERNEL) += sstep.o
endif
# Temporary hack until we have migrated to asm-powerpc
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_CPM2) += rheap.o
endif
arch/powerpc/lib/rheap.c
View file @ ccaa36f7
......@@ -423,17 +423,21 @@ void *rh_detach_region(rh_info_t * info, void *start, int size)
return (void *)s;
}
void *rh_alloc(rh_info_t * info, int size, const char *owner)
void *rh_alloc_align(rh_info_t * info, int size, int alignment, const char *owner)
{
struct list_head *l;
rh_block_t *blk;
rh_block_t *newblk;
void *start;
/* Validate size */
if (size <= 0)
/* Validate size, (must be power of two) */
if (size <= 0 || (alignment & (alignment - 1)) != 0)
return ERR_PTR(-EINVAL);
/* given alignment larger that default rheap alignment */
if (alignment > info->alignment)
size += alignment - 1;
/* Align to configured alignment */
size = (size + (info->alignment - 1)) & ~(info->alignment - 1);
......@@ -476,15 +480,27 @@ void *rh_alloc(rh_info_t * info, int size, const char *owner)
attach_taken_block(info, newblk);
/* for larger alignment return fixed up pointer */
/* this is no problem with the deallocator since */
/* we scan for pointers that lie in the blocks */
if (alignment > info->alignment)
start = (void *)(((unsigned long)start + alignment - 1) &
~(alignment - 1));
return start;
}
void *rh_alloc(rh_info_t * info, int size, const char *owner)
{
return rh_alloc_align(info, size, info->alignment, owner);
}
/* allocate at precisely the given address */
void *rh_alloc_fixed(rh_info_t * info, void *start, int size, const char *owner)
{
struct list_head *l;
rh_block_t *blk, *newblk1, *newblk2;
unsigned long s, e, m, bs, be;
unsigned long s, e, m, bs = 0, be = 0;
/* Validate size */
if (size <= 0)
......
arch/powerpc/math-emu/Makefile
View file @ ccaa36f7
......@@ -11,3 +11,6 @@ obj-$(CONFIG_MATH_EMULATION) += fabs.o fadd.o fadds.o fcmpo.o fcmpu.o \
mcrfs.o mffs.o mtfsb0.o mtfsb1.o \
mtfsf.o mtfsfi.o stfiwx.o stfs.o \
udivmodti4.o
CFLAGS_fabs.o = -fno-builtin-fabs
CFLAGS_math.o = -fno-builtin-fabs
arch/powerpc/oprofile/backtrace.c
View file @ ccaa36f7
......@@ -11,6 +11,7 @@
#include <linux/sched.h>
#include <asm/processor.h>
#include <asm/uaccess.h>
#include <asm/compat.h>
#define STACK_SP(STACK) *(STACK)
......@@ -26,8 +27,9 @@
static unsigned int user_getsp32(unsigned int sp, int is_first)
{
unsigned int stack_frame[2];
void __user *p = compat_ptr(sp);
if (!access_ok(VERIFY_READ, sp, sizeof(stack_frame)))
if (!access_ok(VERIFY_READ, p, sizeof(stack_frame)))
return 0;
/*
......@@ -35,8 +37,7 @@ static unsigned int user_getsp32(unsigned int sp, int is_first)
* which means that we've done all that we can do from
* interrupt context.
*/
if (__copy_from_user_inatomic(stack_frame, (void *)(long)sp,
sizeof(stack_frame)))
if (__copy_from_user_inatomic(stack_frame, p, sizeof(stack_frame)))
return 0;
if (!is_first)
......@@ -54,10 +55,10 @@ static unsigned long user_getsp64(unsigned long sp, int is_first)
{
unsigned long stack_frame[3];
if (!access_ok(VERIFY_READ, sp, sizeof(stack_frame)))
if (!access_ok(VERIFY_READ, (void __user *)sp, sizeof(stack_frame)))
return 0;
if (__copy_from_user_inatomic(stack_frame, (void *)sp,
if (__copy_from_user_inatomic(stack_frame, (void __user *)sp,
sizeof(stack_frame)))
return 0;
......
arch/powerpc/platforms/83xx/mpc834x_itx.c
View file @ ccaa36f7
......@@ -109,6 +109,10 @@ static int __init mpc834x_itx_probe(void)
return 1;
}
#ifdef CONFIG_RTC_CLASS
late_initcall(rtc_class_hookup);
#endif
define_machine(mpc834x_itx) {
.name = "MPC834x ITX",
.probe = mpc834x_itx_probe,
......
arch/powerpc/platforms/85xx/Kconfig
View file @ ccaa36f7
......@@ -11,6 +11,12 @@ config MPC8540_ADS
help
This option enables support for the MPC 8540 ADS board
config MPC8560_ADS
bool "Freescale MPC8560 ADS"
select DEFAULT_UIMAGE
help
This option enables support for the MPC 8560 ADS board
config MPC85xx_CDS
bool "Freescale MPC85xx CDS"
select DEFAULT_UIMAGE
......@@ -25,6 +31,11 @@ config MPC8540
select PPC_INDIRECT_PCI
default y if MPC8540_ADS || MPC85xx_CDS
config MPC8560
bool
select PPC_INDIRECT_PCI
default y if MPC8560_ADS
config PPC_INDIRECT_PCI_BE
bool
depends on PPC_85xx
......@@ -34,4 +45,14 @@ config MPIC
bool
default y
config CPM2
bool
depends on MPC8560
default y
help
The CPM2 (Communications Processor Module) is a coprocessor on
embedded CPUs made by Motorola. Selecting this option means that
you wish to build a kernel for a machine with a CPM2 coprocessor
on it.
endmenu
arch/powerpc/platforms/85xx/Makefile
View file @ ccaa36f7
......@@ -3,4 +3,5 @@
#
obj-$(CONFIG_PPC_85xx) += misc.o pci.o
obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
arch/powerpc/platforms/85xx/mpc85xx_ads.c
View file @ ccaa36f7
......@@ -32,6 +32,13 @@
#include <sysdev/fsl_soc.h>
#include "mpc85xx.h"
#ifdef CONFIG_CPM2
#include <linux/fs_enet_pd.h>
#include <asm/cpm2.h>
#include <sysdev/cpm2_pic.h>
#include <asm/fs_pd.h>
#endif
#ifndef CONFIG_PCI
unsigned long isa_io_base = 0;
unsigned long isa_mem_base = 0;
......@@ -57,12 +64,29 @@ mpc85xx_pcibios_fixup(void)
}
#endif /* CONFIG_PCI */
#ifdef CONFIG_CPM2
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc,
struct pt_regs *regs)
{
int cascade_irq;
while ((cascade_irq = cpm2_get_irq(regs)) >= 0) {
generic_handle_irq(cascade_irq, regs);
}
desc->chip->eoi(irq);
}
#endif /* CONFIG_CPM2 */
void __init mpc85xx_ads_pic_init(void)
{
struct mpic *mpic;
struct resource r;
struct device_node *np = NULL;
#ifdef CONFIG_CPM2
int irq;
#endif
np = of_find_node_by_type(np, "open-pic");
......@@ -104,11 +128,103 @@ void __init mpc85xx_ads_pic_init(void)
mpic_assign_isu(mpic, 14, r.start + 0x10100);
mpic_init(mpic);
#ifdef CONFIG_CPM2
/* Setup CPM2 PIC */
np = of_find_node_by_type(NULL, "cpm-pic");
if (np == NULL) {
printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
return;
}
irq = irq_of_parse_and_map(np, 0);
cpm2_pic_init(np);
set_irq_chained_handler(irq, cpm2_cascade);
#endif
}
/*
* Setup the architecture
*/
#ifdef CONFIG_CPM2
void init_fcc_ioports(struct fs_platform_info *fpi)
{
struct io_port *io = cpm2_map(im_ioport);
int fcc_no = fs_get_fcc_index(fpi->fs_no);
int target;
u32 tempval;
switch(fcc_no) {
case 1:
tempval = in_be32(&io->iop_pdirb);
tempval &= ~PB2_DIRB0;
tempval |= PB2_DIRB1;
out_be32(&io->iop_pdirb, tempval);
tempval = in_be32(&io->iop_psorb);
tempval &= ~PB2_PSORB0;
tempval |= PB2_PSORB1;
out_be32(&io->iop_psorb, tempval);
tempval = in_be32(&io->iop_pparb);
tempval |= (PB2_DIRB0 | PB2_DIRB1);
out_be32(&io->iop_pparb, tempval);
target = CPM_CLK_FCC2;
break;
case 2:
tempval = in_be32(&io->iop_pdirb);
tempval &= ~PB3_DIRB0;
tempval |= PB3_DIRB1;
out_be32(&io->iop_pdirb, tempval);
tempval = in_be32(&io->iop_psorb);
tempval &= ~PB3_PSORB0;
tempval |= PB3_PSORB1;
out_be32(&io->iop_psorb, tempval);
tempval = in_be32(&io->iop_pparb);
tempval |= (PB3_DIRB0 | PB3_DIRB1);
out_be32(&io->iop_pparb, tempval);
tempval = in_be32(&io->iop_pdirc);
tempval |= PC3_DIRC1;
out_be32(&io->iop_pdirc, tempval);
tempval = in_be32(&io->iop_pparc);
tempval |= PC3_DIRC1;
out_be32(&io->iop_pparc, tempval);
target = CPM_CLK_FCC3;
break;
default:
printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
return;
}
/* Port C has clocks...... */
tempval = in_be32(&io->iop_psorc);
tempval &= ~(PC_CLK(fpi->clk_rx - 8) | PC_CLK(fpi->clk_tx - 8));
out_be32(&io->iop_psorc, tempval);
tempval = in_be32(&io->iop_pdirc);
tempval &= ~(PC_CLK(fpi->clk_rx - 8) | PC_CLK(fpi->clk_tx - 8));
out_be32(&io->iop_pdirc, tempval);
tempval = in_be32(&io->iop_pparc);
tempval |= (PC_CLK(fpi->clk_rx - 8) | PC_CLK(fpi->clk_tx - 8));
out_be32(&io->iop_pparc, tempval);
cpm2_unmap(io);
/* Configure Serial Interface clock routing.
* First, clear FCC bits to zero,
* then set the ones we want.
*/
cpm2_clk_setup(target, fpi->clk_rx, CPM_CLK_RX);
cpm2_clk_setup(target, fpi->clk_tx, CPM_CLK_TX);
}
#endif
static void __init mpc85xx_ads_setup_arch(void)
{
struct device_node *cpu;
......@@ -131,6 +247,10 @@ static void __init mpc85xx_ads_setup_arch(void)
of_node_put(cpu);
}
#ifdef CONFIG_CPM2
cpm2_reset();
#endif
#ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
add_bridge(np);
......
arch/powerpc/platforms/85xx/mpc85xx_ads.h 0 → 100644
View file @ ccaa36f7
/*
* MPC85xx ADS board definitions
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2004 Freescale Semiconductor Inc.
*
* 2006 (c) MontaVista Software, Inc.
* Vitaly Bordug <vbordug@ru.mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MACH_MPC85XXADS_H
#define __MACH_MPC85XXADS_H
#include <linux/config.h>
#include <linux/initrd.h>
#include <sysdev/fsl_soc.h>
#define BCSR_ADDR ((uint)0xf8000000)
#define BCSR_SIZE ((uint)(32 * 1024))
#ifdef CONFIG_CPM2
#define MPC85xx_CPM_OFFSET (0x80000)
#define CPM_MAP_ADDR (get_immrbase() + MPC85xx_CPM_OFFSET)
#define CPM_IRQ_OFFSET 60
#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
/* FCC1 Clock Source Configuration. These can be
* redefined in the board specific file.
* Can only choose from CLK9-12 */
#define F1_RXCLK 12
#define F1_TXCLK 11
/* FCC2 Clock Source Configuration. These can be
* redefined in the board specific file.
* Can only choose from CLK13-16 */
#define F2_RXCLK 13
#define F2_TXCLK 14
/* FCC3 Clock Source Configuration. These can be
* redefined in the board specific file.
* Can only choose from CLK13-16 */
#define F3_RXCLK 15
#define F3_TXCLK 16
#endif /* CONFIG_CPM2 */
#endif /* __MACH_MPC85XXADS_H */
arch/powerpc/platforms/cell/spu_base.c
View file @ ccaa36f7
......@@ -538,7 +538,7 @@ static void __iomem * __init map_spe_prop(struct spu *spu,
const void *p;
int proplen;
void* ret = NULL;
void __iomem *ret = NULL;
int err = 0;
p = get_property(n, name, &proplen);
......@@ -562,7 +562,7 @@ static void spu_unmap(struct spu *spu)
iounmap(spu->priv2);
iounmap(spu->priv1);
iounmap(spu->problem);
iounmap((u8 __iomem *)spu->local_store);
iounmap((__force u8 __iomem *)spu->local_store);
}
/* This function shall be abstracted for HV platforms */
......
arch/powerpc/platforms/cell/spufs/file.c
View file @ ccaa36f7
......@@ -1342,7 +1342,7 @@ static u64 spufs_id_get(void *data)
return num;
}
DEFINE_SIMPLE_ATTRIBUTE(spufs_id_ops, spufs_id_get, 0, "0x%llx\n")
DEFINE_SIMPLE_ATTRIBUTE(spufs_id_ops, spufs_id_get, NULL, "0x%llx\n")
struct tree_descr spufs_dir_contents[] = {
{ "mem", &spufs_mem_fops, 0666, },
......
arch/powerpc/platforms/cell/spufs/hw_ops.c
View file @ ccaa36f7
......@@ -234,7 +234,7 @@ static void spu_hw_runcntl_stop(struct spu_context *ctx)
static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode)
{
struct spu_problem *prob = ctx->spu->problem;
struct spu_problem __iomem *prob = ctx->spu->problem;
int ret;
spin_lock_irq(&ctx->spu->register_lock);
......@@ -263,7 +263,7 @@ static int spu_hw_send_mfc_command(struct spu_context *ctx,
struct mfc_dma_command *cmd)
{
u32 status;
struct spu_problem *prob = ctx->spu->problem;
struct spu_problem __iomem *prob = ctx->spu->problem;
spin_lock_irq(&ctx->spu->register_lock);
out_be32(&prob->mfc_lsa_W, cmd->lsa);
......
arch/powerpc/platforms/maple/pci.c
View file @ ccaa36f7
......@@ -96,14 +96,14 @@ static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
1UL;
}
static unsigned long u3_agp_cfg_access(struct pci_controller* hose,
static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,
u8 bus, u8 dev_fn, u8 offset)
{
unsigned int caddr;
if (bus == hose->first_busno) {
if (dev_fn < (11 << 3))
return 0;
return NULL;
caddr = u3_agp_cfa0(dev_fn, offset);
} else
caddr = u3_agp_cfa1(bus, dev_fn, offset);
......@@ -114,14 +114,14 @@ static unsigned long u3_agp_cfg_access(struct pci_controller* hose,
} while (in_le32(hose->cfg_addr) != caddr);
offset &= 0x07;
return ((unsigned long)hose->cfg_data) + offset;
return hose->cfg_data + offset;
}
static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
int offset, int len, u32 *val)
{
struct pci_controller *hose;
unsigned long addr;
volatile void __iomem *addr;
hose = pci_bus_to_host(bus);
if (hose == NULL)
......@@ -136,13 +136,13 @@ static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
*/
switch (len) {
case 1:
*val = in_8((u8 *)addr);
*val = in_8(addr);
break;
case 2:
*val = in_le16((u16 *)addr);
*val = in_le16(addr);
break;
default:
*val = in_le32((u32 *)addr);
*val = in_le32(addr);
break;
}
return PCIBIOS_SUCCESSFUL;
......@@ -152,7 +152,7 @@ static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
int offset, int len, u32 val)
{
struct pci_controller *hose;
unsigned long addr;
volatile void __iomem *addr;
hose = pci_bus_to_host(bus);
if (hose == NULL)
......@@ -167,16 +167,16 @@ static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
*/
switch (len) {
case 1:
out_8((u8 *)addr, val);
(void) in_8((u8 *)addr);
out_8(addr, val);
(void) in_8(addr);
break;
case 2:
out_le16((u16 *)addr, val);
(void) in_le16((u16 *)addr);
out_le16(addr, val);
(void) in_le16(addr);
break;
default:
out_le32((u32 *)addr, val);
(void) in_le32((u32 *)addr);
out_le32(addr, val);
(void) in_le32(addr);
break;
}
return PCIBIOS_SUCCESSFUL;
......@@ -198,22 +198,22 @@ static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
}
static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
u8 bus, u8 devfn, u8 offset)
{
if (bus == hose->first_busno) {
if (PCI_SLOT(devfn) == 0)
return 0;
return ((unsigned long)hose->cfg_data) + u3_ht_cfa0(devfn, offset);
return NULL;
return hose->cfg_data + u3_ht_cfa0(devfn, offset);
} else
return ((unsigned long)hose->cfg_data) + u3_ht_cfa1(bus, devfn, offset);
return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
}
static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
int offset, int len, u32 *val)
{
struct pci_controller *hose;
unsigned long addr;
volatile void __iomem *addr;
hose = pci_bus_to_host(bus);
if (hose == NULL)
......@@ -232,13 +232,13 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
*/
switch (len) {
case 1:
*val = in_8((u8 *)addr);
*val = in_8(addr);
break;
case 2:
*val = in_le16((u16 *)addr);
*val = in_le16(addr);
break;
default:
*val = in_le32((u32 *)addr);
*val = in_le32(addr);
break;
}
return PCIBIOS_SUCCESSFUL;
......@@ -248,7 +248,7 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
int offset, int len, u32 val)
{
struct pci_controller *hose;
unsigned long addr;
volatile void __iomem *addr;
hose = pci_bus_to_host(bus);
if (hose == NULL)
......@@ -266,16 +266,16 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
*/
switch (len) {
case 1:
out_8((u8 *)addr, val);
(void) in_8((u8 *)addr);
out_8(addr, val);
(void) in_8(addr);
break;
case 2:
out_le16((u16 *)addr, val);
(void) in_le16((u16 *)addr);
out_le16(addr, val);
(void) in_le16(addr);
break;
default:
out_le32((u32 *)addr, val);
(void) in_le32((u32 *)addr);
out_le32(addr, val);
(void) in_le32(addr);
break;
}
return PCIBIOS_SUCCESSFUL;
......@@ -315,7 +315,7 @@ static void __init setup_u3_ht(struct pci_controller* hose)
* the reg address cell, we shall fix that by killing struct
* reg_property and using some accessor functions instead
*/
hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
hose->cfg_data = ioremap(0xf2000000, 0x02000000);
hose->first_busno = 0;
hose->last_busno = 0xef;
......
arch/powerpc/platforms/pseries/eeh.c
View file @ ccaa36f7
......@@ -225,6 +225,7 @@ static void __eeh_mark_slot (struct device_node *dn, int mode_flag)
void eeh_mark_slot (struct device_node *dn, int mode_flag)
{
struct pci_dev *dev;
dn = find_device_pe (dn);
/* Back up one, since config addrs might be shared */
......@@ -232,6 +233,12 @@ void eeh_mark_slot (struct device_node *dn, int mode_flag)
dn = dn->parent;
PCI_DN(dn)->eeh_mode |= mode_flag;
/* Mark the pci device too */
dev = PCI_DN(dn)->pcidev;
if (dev)
dev->error_state = pci_channel_io_frozen;
__eeh_mark_slot (dn->child, mode_flag);
}
......
arch/powerpc/platforms/pseries/setup.c
View file @ ccaa36f7
......@@ -477,7 +477,6 @@ static void pseries_dedicated_idle_sleep(void)
{
unsigned int cpu = smp_processor_id();
unsigned long start_snooze;
unsigned long *smt_snooze_delay = &__get_cpu_var(smt_snooze_delay);
/*
* Indicate to the HV that we are idle. Now would be
......@@ -490,9 +489,9 @@ static void pseries_dedicated_idle_sleep(void)
* has been checked recently. If we should poll for a little
* while, do so.
*/
if (*smt_snooze_delay) {
if (__get_cpu_var(smt_snooze_delay)) {
start_snooze = get_tb() +
*smt_snooze_delay * tb_ticks_per_usec;
__get_cpu_var(smt_snooze_delay) * tb_ticks_per_usec;
local_irq_enable();
set_thread_flag(TIF_POLLING_NRFLAG);
......@@ -512,24 +511,7 @@ static void pseries_dedicated_idle_sleep(void)
goto out;
}
/*
* If not SMT, cede processor. If CPU is running SMT
* cede if the other thread is not idle, so that it can
* go single-threaded. If the other thread is idle,
* we ask the hypervisor if it has pending work it
* wants to do and cede if it does. Otherwise we keep
* polling in order to reduce interrupt latency.
*
* Doing the cede when the other thread is active will
* result in this thread going dormant, meaning the other
* thread gets to run in single-threaded (ST) mode, which
* is slightly faster than SMT mode with this thread at
* very low priority. The cede enables interrupts, which
* doesn't matter here.
*/
if (!cpu_has_feature(CPU_FTR_SMT) || !lppaca[cpu ^ 1].idle
|| poll_pending() == H_PENDING)
cede_processor();
cede_processor();
out:
HMT_medium();
......
arch/powerpc/sysdev/Makefile
View file @ ccaa36f7
......@@ -17,3 +17,8 @@ ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_I8259) += i8259.o
obj-$(CONFIG_PPC_83xx) += ipic.o
endif
# Temporary hack until we have migrated to asm-powerpc
ifeq ($(ARCH),powerpc)
obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
endif
arch/powerpc/sysdev/cpm2_common.c 0 → 100644
View file @ ccaa36f7
/*
* General Purpose functions for the global management of the
* 8260 Communication Processor Module.
* Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
* 2.3.99 Updates
*
* 2006 (c) MontaVista Software, Inc.
* Vitaly Bordug <vbordug@ru.mvista.com>
* Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/*
*
* In addition to the individual control of the communication
* channels, there are a few functions that globally affect the
* communication processor.
*
* Buffer descriptors must be allocated from the dual ported memory
* space. The allocator for that is here. When the communication
* process is reset, we reclaim the memory available. There is
* currently no deallocator for this memory.
*/
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mpc8260.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/cpm2.h>
#include <asm/rheap.h>
#include <asm/fs_pd.h>
#include <sysdev/fsl_soc.h>
static void cpm2_dpinit(void);
cpm_cpm2_t *cpmp; /* Pointer to comm processor space */
/* We allocate this here because it is used almost exclusively for
* the communication processor devices.
*/
cpm2_map_t *cpm2_immr;
intctl_cpm2_t *cpm2_intctl;
#define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
of space for CPM as it is larger
than on PQ2 */
void
cpm2_reset(void)
{
cpm2_immr = (cpm2_map_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
cpm2_intctl = cpm2_map(im_intctl);
/* Reclaim the DP memory for our use.
*/
cpm2_dpinit();
/* Tell everyone where the comm processor resides.
*/
cpmp = &cpm2_immr->im_cpm;
}
/* Set a baud rate generator. This needs lots of work. There are
* eight BRGs, which can be connected to the CPM channels or output
* as clocks. The BRGs are in two different block of internal
* memory mapped space.
* The baud rate clock is the system clock divided by something.
* It was set up long ago during the initial boot phase and is
* is given to us.
* Baud rate clocks are zero-based in the driver code (as that maps
* to port numbers). Documentation uses 1-based numbering.
*/
#define BRG_INT_CLK (get_brgfreq())
#define BRG_UART_CLK (BRG_INT_CLK/16)
/* This function is used by UARTS, or anything else that uses a 16x
* oversampled clock.
*/
void
cpm_setbrg(uint brg, uint rate)
{
volatile uint *bp;
/* This is good enough to get SMCs running.....
*/
if (brg < 4) {
bp = cpm2_map_size(im_brgc1, 16);
} else {
bp = cpm2_map_size(im_brgc5, 16);
brg -= 4;
}
bp += brg;
*bp = ((BRG_UART_CLK / rate) << 1) | CPM_BRG_EN;
cpm2_unmap(bp);
}
/* This function is used to set high speed synchronous baud rate
* clocks.
*/
void
cpm2_fastbrg(uint brg, uint rate, int div16)
{
volatile uint *bp;
if (brg < 4) {
bp = cpm2_map_size(im_brgc1, 16);
}
else {
bp = cpm2_map_size(im_brgc5, 16);
brg -= 4;
}
bp += brg;
*bp = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
if (div16)
*bp |= CPM_BRG_DIV16;
cpm2_unmap(bp);
}
int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
{
int ret = 0;
int shift;
int i, bits = 0;
cpmux_t *im_cpmux;
u32 *reg;
u32 mask = 7;
u8 clk_map [24][3] = {
{CPM_CLK_FCC1, CPM_BRG5, 0},
{CPM_CLK_FCC1, CPM_BRG6, 1},
{CPM_CLK_FCC1, CPM_BRG7, 2},
{CPM_CLK_FCC1, CPM_BRG8, 3},
{CPM_CLK_FCC1, CPM_CLK9, 4},
{CPM_CLK_FCC1, CPM_CLK10, 5},
{CPM_CLK_FCC1, CPM_CLK11, 6},
{CPM_CLK_FCC1, CPM_CLK12, 7},
{CPM_CLK_FCC2, CPM_BRG5, 0},
{CPM_CLK_FCC2, CPM_BRG6, 1},
{CPM_CLK_FCC2, CPM_BRG7, 2},
{CPM_CLK_FCC2, CPM_BRG8, 3},
{CPM_CLK_FCC2, CPM_CLK13, 4},
{CPM_CLK_FCC2, CPM_CLK14, 5},
{CPM_CLK_FCC2, CPM_CLK15, 6},
{CPM_CLK_FCC2, CPM_CLK16, 7},
{CPM_CLK_FCC3, CPM_BRG5, 0},
{CPM_CLK_FCC3, CPM_BRG6, 1},
{CPM_CLK_FCC3, CPM_BRG7, 2},
{CPM_CLK_FCC3, CPM_BRG8, 3},
{CPM_CLK_FCC3, CPM_CLK13, 4},
{CPM_CLK_FCC3, CPM_CLK14, 5},
{CPM_CLK_FCC3, CPM_CLK15, 6},
{CPM_CLK_FCC3, CPM_CLK16, 7}
};
im_cpmux = cpm2_map(im_cpmux);
switch (target) {
case CPM_CLK_SCC1:
reg = &im_cpmux->cmx_scr;
shift = 24;
case CPM_CLK_SCC2:
reg = &im_cpmux->cmx_scr;
shift = 16;
break;
case CPM_CLK_SCC3:
reg = &im_cpmux->cmx_scr;
shift = 8;
break;
case CPM_CLK_SCC4:
reg = &im_cpmux->cmx_scr;
shift = 0;
break;
case CPM_CLK_FCC1:
reg = &im_cpmux->cmx_fcr;
shift = 24;
break;
case CPM_CLK_FCC2:
reg = &im_cpmux->cmx_fcr;
shift = 16;
break;
case CPM_CLK_FCC3:
reg = &im_cpmux->cmx_fcr;
shift = 8;
break;
default:
printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
return -EINVAL;
}
if (mode == CPM_CLK_RX)
shift +=3;
for (i=0; i<24; i++) {
if (clk_map[i][0] == target && clk_map[i][1] == clock) {
bits = clk_map[i][2];
break;
}
}
if (i == sizeof(clk_map)/3)
ret = -EINVAL;
bits <<= shift;
mask <<= shift;
out_be32(reg, (in_be32(reg) & ~mask) | bits);
cpm2_unmap(im_cpmux);
return ret;
}
/*
* dpalloc / dpfree bits.
*/
static spinlock_t cpm_dpmem_lock;
/* 16 blocks should be enough to satisfy all requests
* until the memory subsystem goes up... */
static rh_block_t cpm_boot_dpmem_rh_block[16];
static rh_info_t cpm_dpmem_info;
static u8* im_dprambase;
static void cpm2_dpinit(void)
{
spin_lock_init(&cpm_dpmem_lock);
im_dprambase = ioremap(CPM_MAP_ADDR, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE);
/* initialize the info header */
rh_init(&cpm_dpmem_info, 1,
sizeof(cpm_boot_dpmem_rh_block) /
sizeof(cpm_boot_dpmem_rh_block[0]),
cpm_boot_dpmem_rh_block);
/* Attach the usable dpmem area */
/* XXX: This is actually crap. CPM_DATAONLY_BASE and
* CPM_DATAONLY_SIZE is only a subset of the available dpram. It
* varies with the processor and the microcode patches activated.
* But the following should be at least safe.
*/
rh_attach_region(&cpm_dpmem_info, (void *)CPM_DATAONLY_BASE,
CPM_DATAONLY_SIZE);
}
/* This function returns an index into the DPRAM area.
*/
uint cpm_dpalloc(uint size, uint align)
{
void *start;
unsigned long flags;
spin_lock_irqsave(&cpm_dpmem_lock, flags);
cpm_dpmem_info.alignment = align;
start = rh_alloc(&cpm_dpmem_info, size, "commproc");
spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
return (uint)start;
}
EXPORT_SYMBOL(cpm_dpalloc);
int cpm_dpfree(uint offset)
{
int ret;
unsigned long flags;
spin_lock_irqsave(&cpm_dpmem_lock, flags);
ret = rh_free(&cpm_dpmem_info, (void *)offset);
spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
return ret;
}
EXPORT_SYMBOL(cpm_dpfree);
/* not sure if this is ever needed */
uint cpm_dpalloc_fixed(uint offset, uint size, uint align)
{
void *start;
unsigned long flags;
spin_lock_irqsave(&cpm_dpmem_lock, flags);
cpm_dpmem_info.alignment = align;
start = rh_alloc_fixed(&cpm_dpmem_info, (void *)offset, size, "commproc");
spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
return (uint)start;
}
EXPORT_SYMBOL(cpm_dpalloc_fixed);
void cpm_dpdump(void)
{
rh_dump(&cpm_dpmem_info);
}
EXPORT_SYMBOL(cpm_dpdump);
void *cpm_dpram_addr(uint offset)
{
return (void *)(im_dprambase + offset);
}
EXPORT_SYMBOL(cpm_dpram_addr);
arch/powerpc/sysdev/cpm2_pic.c 0 → 100644
View file @ ccaa36f7
/*
* Platform information definitions.
*
* Copied from arch/ppc/syslib/cpm2_pic.c with minor subsequent updates
* to make in work in arch/powerpc/. Original (c) belongs to Dan Malek.
*
* Author: Vitaly Bordug <vbordug@ru.mvista.com>
*
* 1999-2001 (c) Dan Malek <dan@embeddedalley.com>
* 2006 (c) MontaVista Software, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/* The CPM2 internal interrupt controller. It is usually
* the only interrupt controller.
* There are two 32-bit registers (high/low) for up to 64
* possible interrupts.
*
* Now, the fun starts.....Interrupt Numbers DO NOT MAP
* in a simple arithmetic fashion to mask or pending registers.
* That is, interrupt 4 does not map to bit position 4.
* We create two tables, indexed by vector number, to indicate
* which register to use and which bit in the register to use.
*/
#include <linux/stddef.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/irq.h>
#include <asm/immap_cpm2.h>
#include <asm/mpc8260.h>
#include <asm/io.h>
#include <asm/prom.h>
#include "cpm2_pic.h"
static struct device_node *cpm2_pic_node;
static struct irq_host *cpm2_pic_host;
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
static const u_char irq_to_siureg[] = {
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
};
/* bit numbers do not match the docs, these are precomputed so the bit for
* a given irq is (1 << irq_to_siubit[irq]) */
static const u_char irq_to_siubit[] = {
0, 15, 14, 13, 12, 11, 10, 9,
8, 7, 6, 5, 4, 3, 2, 1,
2, 1, 0, 14, 13, 12, 11, 10,
9, 8, 7, 6, 5, 4, 3, 0,
31, 30, 29, 28, 27, 26, 25, 24,
23, 22, 21, 20, 19, 18, 17, 16,
16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27, 28, 29, 30, 31,
};
static void cpm2_mask_irq(unsigned int irq_nr)
{
int bit, word;
volatile uint *simr;
irq_nr -= CPM_IRQ_OFFSET;
bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr];
simr = &(cpm2_intctl->ic_simrh);
ppc_cached_irq_mask[word] &= ~(1 << bit);
simr[word] = ppc_cached_irq_mask[word];
}
static void cpm2_unmask_irq(unsigned int irq_nr)
{
int bit, word;
volatile uint *simr;
irq_nr -= CPM_IRQ_OFFSET;
bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr];
simr = &(cpm2_intctl->ic_simrh);
ppc_cached_irq_mask[word] |= 1 << bit;
simr[word] = ppc_cached_irq_mask[word];
}
static void cpm2_mask_and_ack(unsigned int irq_nr)
{
int bit, word;
volatile uint *simr, *sipnr;
irq_nr -= CPM_IRQ_OFFSET;
bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr];
simr = &(cpm2_intctl->ic_simrh);
sipnr = &(cpm2_intctl->ic_sipnrh);
ppc_cached_irq_mask[word] &= ~(1 << bit);
simr[word] = ppc_cached_irq_mask[word];
sipnr[word] = 1 << bit;
}
static void cpm2_end_irq(unsigned int irq_nr)
{
int bit, word;
volatile uint *simr;
if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
&& irq_desc[irq_nr].action) {
irq_nr -= CPM_IRQ_OFFSET;
bit = irq_to_siubit[irq_nr];
word = irq_to_siureg[irq_nr];
simr = &(cpm2_intctl->ic_simrh);
ppc_cached_irq_mask[word] |= 1 << bit;
simr[word] = ppc_cached_irq_mask[word];
/*
* Work around large numbers of spurious IRQs on PowerPC 82xx
* systems.
*/
mb();
}
}
static struct irq_chip cpm2_pic = {
.typename = " CPM2 SIU ",
.enable = cpm2_unmask_irq,
.disable = cpm2_mask_irq,
.unmask = cpm2_unmask_irq,
.mask_ack = cpm2_mask_and_ack,
.end = cpm2_end_irq,
};
int cpm2_get_irq(struct pt_regs *regs)
{
int irq;
unsigned long bits;
/* For CPM2, read the SIVEC register and shift the bits down
* to get the irq number. */
bits = cpm2_intctl->ic_sivec;
irq = bits >> 26;
if (irq == 0)
return(-1);
return irq+CPM_IRQ_OFFSET;
}
static int cpm2_pic_host_match(struct irq_host *h, struct device_node *node)
{
return cpm2_pic_node == NULL || cpm2_pic_node == node;
}
static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
get_irq_desc(virq)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
return 0;
}
static void cpm2_host_unmap(struct irq_host *h, unsigned int virq)
{
/* Make sure irq is masked in hardware */
cpm2_mask_irq(virq);
/* remove chip and handler */
set_irq_chip_and_handler(virq, NULL, NULL);
}
static int cpm2_pic_host_xlate(struct irq_host *h, struct device_node *ct,
u32 *intspec, unsigned int intsize,
irq_hw_number_t *out_hwirq, unsigned int *out_flags)
{
static const unsigned char map_cpm2_senses[4] = {
IRQ_TYPE_LEVEL_LOW,
IRQ_TYPE_LEVEL_HIGH,
IRQ_TYPE_EDGE_FALLING,
IRQ_TYPE_EDGE_RISING,
};
*out_hwirq = intspec[0];
if (intsize > 1 && intspec[1] < 4)
*out_flags = map_cpm2_senses[intspec[1]];
else
*out_flags = IRQ_TYPE_NONE;
return 0;
}
static struct irq_host_ops cpm2_pic_host_ops = {
.match = cpm2_pic_host_match,
.map = cpm2_pic_host_map,
.unmap = cpm2_host_unmap,
.xlate = cpm2_pic_host_xlate,
};
void cpm2_pic_init(struct device_node *node)
{
int i;
/* Clear the CPM IRQ controller, in case it has any bits set
* from the bootloader
*/
/* Mask out everything */
cpm2_intctl->ic_simrh = 0x00000000;
cpm2_intctl->ic_simrl = 0x00000000;
wmb();
/* Ack everything */
cpm2_intctl->ic_sipnrh = 0xffffffff;
cpm2_intctl->ic_sipnrl = 0xffffffff;
wmb();
/* Dummy read of the vector */
i = cpm2_intctl->ic_sivec;
rmb();
/* Initialize the default interrupt mapping priorities,
* in case the boot rom changed something on us.
*/
cpm2_intctl->ic_sicr = 0;
cpm2_intctl->ic_scprrh = 0x05309770;
cpm2_intctl->ic_scprrl = 0x05309770;
/* create a legacy host */
if (node)
cpm2_pic_node = of_node_get(node);
cpm2_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &cpm2_pic_host_ops, 64);
if (cpm2_pic_host == NULL) {
printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
return;
}
}
arch/powerpc/sysdev/cpm2_pic.h 0 → 100644
View file @ ccaa36f7
#ifndef _PPC_KERNEL_CPM2_H
#define _PPC_KERNEL_CPM2_H
extern intctl_cpm2_t *cpm2_intctl;
extern int cpm2_get_irq(struct pt_regs *regs);
extern void cpm2_pic_init(struct device_node*);
#endif /* _PPC_KERNEL_CPM2_H */
arch/powerpc/sysdev/fsl_soc.c
View file @ ccaa36f7
......@@ -3,6 +3,9 @@
*
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
*
* 2006 (c) MontaVista Software, Inc.
* Vitaly Bordug <vbordug@ru.mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
......@@ -20,15 +23,20 @@
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
#include <linux/fs_enet_pd.h>
#include <linux/fs_uart_pd.h>
#include <asm/system.h>
#include <asm/atomic.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/time.h>
#include <asm/prom.h>
#include <sysdev/fsl_soc.h>
#include <mm/mmu_decl.h>
#include <asm/cpm2.h>
extern void init_fcc_ioports(struct fs_platform_info*);
static phys_addr_t immrbase = -1;
phys_addr_t get_immrbase(void)
......@@ -42,7 +50,9 @@ phys_addr_t get_immrbase(void)
if (soc) {
unsigned int size;
const void *prop = get_property(soc, "reg", &size);
immrbase = of_translate_address(soc, prop);
if (prop)
immrbase = of_translate_address(soc, prop);
of_node_put(soc);
};
......@@ -51,6 +61,59 @@ phys_addr_t get_immrbase(void)
EXPORT_SYMBOL(get_immrbase);
#ifdef CONFIG_CPM2
static u32 brgfreq = -1;
u32 get_brgfreq(void)
{
struct device_node *node;
if (brgfreq != -1)
return brgfreq;
node = of_find_node_by_type(NULL, "cpm");
if (node) {
unsigned int size;
const unsigned int *prop = get_property(node, "brg-frequency",
&size);
if (prop)
brgfreq = *prop;
of_node_put(node);
};
return brgfreq;
}
EXPORT_SYMBOL(get_brgfreq);
static u32 fs_baudrate = -1;
u32 get_baudrate(void)
{
struct device_node *node;
if (fs_baudrate != -1)
return fs_baudrate;
node = of_find_node_by_type(NULL, "serial");
if (node) {
unsigned int size;
const unsigned int *prop = get_property(node, "current-speed",
&size);
if (prop)
fs_baudrate = *prop;
of_node_put(node);
};
return fs_baudrate;
}
EXPORT_SYMBOL(get_baudrate);
#endif /* CONFIG_CPM2 */
static int __init gfar_mdio_of_init(void)
{
struct device_node *np;
......@@ -85,8 +148,11 @@ static int __init gfar_mdio_of_init(void)
mdio_data.irq[k] = -1;
while ((child = of_get_next_child(np, child)) != NULL) {
const u32 *id = get_property(child, "reg", NULL);
mdio_data.irq[*id] = irq_of_parse_and_map(child, 0);
int irq = irq_of_parse_and_map(child, 0);
if (irq != NO_IRQ) {
const u32 *id = get_property(child, "reg", NULL);
mdio_data.irq[*id] = irq;
}
}
ret =
......@@ -128,7 +194,7 @@ static int __init gfar_of_init(void)
const char *model;
const void *mac_addr;
const phandle *ph;
int n_res = 1;
int n_res = 2;
memset(r, 0, sizeof(r));
memset(&gfar_data, 0, sizeof(gfar_data));
......@@ -159,7 +225,7 @@ static int __init gfar_of_init(void)
gfar_dev =
platform_device_register_simple("fsl-gianfar", i, &r[0],
n_res + 1);
n_res);
if (IS_ERR(gfar_dev)) {
ret = PTR_ERR(gfar_dev);
......@@ -478,3 +544,208 @@ err:
}
arch_initcall(fsl_usb_of_init);
#ifdef CONFIG_CPM2
static const char fcc_regs[] = "fcc_regs";
static const char fcc_regs_c[] = "fcc_regs_c";
static const char fcc_pram[] = "fcc_pram";
static char bus_id[9][BUS_ID_SIZE];
static int __init fs_enet_of_init(void)
{
struct device_node *np;
unsigned int i;
struct platform_device *fs_enet_dev;
struct resource res;
int ret;
for (np = NULL, i = 0;
(np = of_find_compatible_node(np, "network", "fs_enet")) != NULL;
i++) {
struct resource r[4];
struct device_node *phy, *mdio;
struct fs_platform_info fs_enet_data;
const unsigned int *id, *phy_addr;
const void *mac_addr;
const phandle *ph;
const char *model;
memset(r, 0, sizeof(r));
memset(&fs_enet_data, 0, sizeof(fs_enet_data));
ret = of_address_to_resource(np, 0, &r[0]);
if (ret)
goto err;
r[0].name = fcc_regs;
ret = of_address_to_resource(np, 1, &r[1]);
if (ret)
goto err;
r[1].name = fcc_pram;
ret = of_address_to_resource(np, 2, &r[2]);
if (ret)
goto err;
r[2].name = fcc_regs_c;
r[3].start = r[3].end = irq_of_parse_and_map(np, 0);
r[3].flags = IORESOURCE_IRQ;
fs_enet_dev =
platform_device_register_simple("fsl-cpm-fcc", i, &r[0], 4);
if (IS_ERR(fs_enet_dev)) {
ret = PTR_ERR(fs_enet_dev);
goto err;
}
model = get_property(np, "model", NULL);
if (model == NULL) {
ret = -ENODEV;
goto unreg;
}
mac_addr = get_property(np, "mac-address", NULL);
memcpy(fs_enet_data.macaddr, mac_addr, 6);
ph = get_property(np, "phy-handle", NULL);
phy = of_find_node_by_phandle(*ph);
if (phy == NULL) {
ret = -ENODEV;
goto unreg;
}
phy_addr = get_property(phy, "reg", NULL);
fs_enet_data.phy_addr = *phy_addr;
id = get_property(np, "device-id", NULL);
fs_enet_data.fs_no = *id;
strcpy(fs_enet_data.fs_type, model);
mdio = of_get_parent(phy);
ret = of_address_to_resource(mdio, 0, &res);
if (ret) {
of_node_put(phy);
of_node_put(mdio);
goto unreg;
}
fs_enet_data.clk_rx = *((u32 *) get_property(np, "rx-clock", NULL));
fs_enet_data.clk_tx = *((u32 *) get_property(np, "tx-clock", NULL));
if (strstr(model, "FCC")) {
int fcc_index = *id - 1;
fs_enet_data.dpram_offset = (u32)cpm_dpram_addr(0);
fs_enet_data.rx_ring = 32;
fs_enet_data.tx_ring = 32;
fs_enet_data.rx_copybreak = 240;
fs_enet_data.use_napi = 0;
fs_enet_data.napi_weight = 17;
fs_enet_data.mem_offset = FCC_MEM_OFFSET(fcc_index);
fs_enet_data.cp_page = CPM_CR_FCC_PAGE(fcc_index);
fs_enet_data.cp_block = CPM_CR_FCC_SBLOCK(fcc_index);
snprintf((char*)&bus_id[(*id)], BUS_ID_SIZE, "%x:%02x",
(u32)res.start, fs_enet_data.phy_addr);
fs_enet_data.bus_id = (char*)&bus_id[(*id)];
fs_enet_data.init_ioports = init_fcc_ioports;
}
of_node_put(phy);
of_node_put(mdio);
ret = platform_device_add_data(fs_enet_dev, &fs_enet_data,
sizeof(struct
fs_platform_info));
if (ret)
goto unreg;
}
return 0;
unreg:
platform_device_unregister(fs_enet_dev);
err:
return ret;
}
arch_initcall(fs_enet_of_init);
static const char scc_regs[] = "regs";
static const char scc_pram[] = "pram";
static int __init cpm_uart_of_init(void)
{
struct device_node *np;
unsigned int i;
struct platform_device *cpm_uart_dev;
int ret;
for (np = NULL, i = 0;
(np = of_find_compatible_node(np, "serial", "cpm_uart")) != NULL;
i++) {
struct resource r[3];
struct fs_uart_platform_info cpm_uart_data;
const int *id;
const char *model;
memset(r, 0, sizeof(r));
memset(&cpm_uart_data, 0, sizeof(cpm_uart_data));
ret = of_address_to_resource(np, 0, &r[0]);
if (ret)
goto err;
r[0].name = scc_regs;
ret = of_address_to_resource(np, 1, &r[1]);
if (ret)
goto err;
r[1].name = scc_pram;
r[2].start = r[2].end = irq_of_parse_and_map(np, 0);
r[2].flags = IORESOURCE_IRQ;
cpm_uart_dev =
platform_device_register_simple("fsl-cpm-scc:uart", i, &r[0], 3);
if (IS_ERR(cpm_uart_dev)) {
ret = PTR_ERR(cpm_uart_dev);
goto err;
}
id = get_property(np, "device-id", NULL);
cpm_uart_data.fs_no = *id;
model = (char*)get_property(np, "model", NULL);
strcpy(cpm_uart_data.fs_type, model);
cpm_uart_data.uart_clk = ppc_proc_freq;
cpm_uart_data.tx_num_fifo = 4;
cpm_uart_data.tx_buf_size = 32;
cpm_uart_data.rx_num_fifo = 4;
cpm_uart_data.rx_buf_size = 32;
cpm_uart_data.clk_rx = *((u32 *) get_property(np, "rx-clock", NULL));
cpm_uart_data.clk_tx = *((u32 *) get_property(np, "tx-clock", NULL));
ret =
platform_device_add_data(cpm_uart_dev, &cpm_uart_data,
sizeof(struct
fs_uart_platform_info));
if (ret)
goto unreg;
}
return 0;
unreg:
platform_device_unregister(cpm_uart_dev);
err:
return ret;
}
arch_initcall(cpm_uart_of_init);
#endif /* CONFIG_CPM2 */
arch/powerpc/sysdev/fsl_soc.h
View file @ ccaa36f7
......@@ -5,6 +5,8 @@
#include <asm/mmu.h>
extern phys_addr_t get_immrbase(void);
extern u32 get_brgfreq(void);
extern u32 get_baudrate(void);
#endif
#endif
arch/ppc/boot/utils/mkbugboot.c
View file @ ccaa36f7
......@@ -19,36 +19,13 @@
#include <stdlib.h>
#include <errno.h>
#include <fcntl.h>
#include <netinet/in.h>
#ifdef __sun__
#include <inttypes.h>
#else
#include <stdint.h>
#endif
#ifdef __i386__
#define cpu_to_be32(x) le32_to_cpu(x)
#define cpu_to_be16(x) le16_to_cpu(x)
#else
#define cpu_to_be32(x) (x)
#define cpu_to_be16(x) (x)
#endif
#define cpu_to_le32(x) le32_to_cpu((x))
unsigned long le32_to_cpu(unsigned long x)
{
return (((x & 0x000000ffU) << 24) |
((x & 0x0000ff00U) << 8) |
((x & 0x00ff0000U) >> 8) |
((x & 0xff000000U) >> 24));
}
#define cpu_to_le16(x) le16_to_cpu((x))
unsigned short le16_to_cpu(unsigned short x)
{
return (((x & 0x00ff) << 8) |
((x & 0xff00) >> 8));
}
/* size of read buffer */
#define SIZE 0x1000
......@@ -62,124 +39,109 @@ typedef struct bug_boot_header {
#define HEADER_SIZE sizeof(bug_boot_header_t)
uint32_t copy_image(int32_t in_fd, int32_t out_fd)
void update_checksum(void *buf, size_t size, uint16_t *sum)
{
uint8_t buf[SIZE];
int n;
uint32_t image_size = 0;
uint8_t zero = 0;
lseek(in_fd, ELF_HEADER_SIZE, SEEK_SET);
/* Copy an image while recording its size */
while ( (n = read(in_fd, buf, SIZE)) > 0 )
{
image_size = image_size + n;
write(out_fd, buf, n);
}
/* BUG romboot requires that our size is divisible by 2 */
/* align image to 2 byte boundary */
if (image_size % 2)
{
image_size++;
write(out_fd, &zero, 1);
}
return image_size;
uint32_t csum = *sum;
while (size) {
csum += *(uint16_t *)buf;
if (csum > 0xffff)
csum -= 0xffff;
buf = (uint16_t *)buf + 1;
size -= 2;
}
*sum = csum;
}
void write_bugboot_header(int32_t out_fd, uint32_t boot_size)
uint32_t copy_image(int in_fd, int out_fd, uint16_t *sum)
{
uint8_t header_block[HEADER_SIZE];
bug_boot_header_t *bbh = (bug_boot_header_t *)&header_block[0];
memset(header_block, 0, HEADER_SIZE);
/* Fill in the PPCBUG ROM boot header */
strncpy(bbh->magic_word, "BOOT", 4); /* PPCBUG magic word */
bbh->entry_offset = cpu_to_be32(HEADER_SIZE); /* Entry address */
bbh->routine_length= cpu_to_be32(HEADER_SIZE+boot_size+2); /* Routine length */
strncpy(bbh->routine_name, "LINUXROM", 8); /* Routine name */
/* Output the header and bootloader to the file */
write(out_fd, header_block, HEADER_SIZE);
uint8_t buf[SIZE];
int offset = 0;
int n;
uint32_t image_size = 0;
lseek(in_fd, ELF_HEADER_SIZE, SEEK_SET);
/* Copy an image while recording its size */
while ( (n = read(in_fd, buf + offset, SIZE - offset)) > 0 ) {
n += offset;
offset = n & 1;
n -= offset;
image_size = image_size + n;
/* who's going to deal with short writes? */
write(out_fd, buf, n);
update_checksum(buf, n, sum);
if (offset)
buf[0] = buf[n];
}
/* BUG romboot requires that our size is divisible by 2 */
/* align image to 2 byte boundary */
if (offset) {
image_size += 2;
buf[1] = '\0';
write(out_fd, buf, 2);
update_checksum(buf, 2, sum);
}
return image_size;
}
uint16_t calc_checksum(int32_t bug_fd)
void write_bugboot_header(int out_fd, uint32_t boot_size, uint16_t *sum)
{
uint32_t checksum_var = 0;
uint8_t buf[2];
int n;
/* Checksum loop */
while ( (n = read(bug_fd, buf, 2) ) )
{
checksum_var = checksum_var + *(uint16_t *)buf;
/* If we carry out, mask it and add one to the checksum */
if (checksum_var >> 16)
checksum_var = (checksum_var & 0x0000ffff) + 1;
}
return checksum_var;
static bug_boot_header_t bbh = {
.magic_word = "BOOT",
.routine_name = "LINUXROM"
};
/* Fill in the PPCBUG ROM boot header */
bbh.entry_offset = htonl(HEADER_SIZE); /* Entry address */
bbh.routine_length= htonl(HEADER_SIZE+boot_size+2); /* Routine length */
/* Output the header and bootloader to the file */
write(out_fd, &bbh, sizeof(bug_boot_header_t));
update_checksum(&bbh, sizeof(bug_boot_header_t), sum);
}
int main(int argc, char *argv[])
{
int32_t image_fd, bugboot_fd;
int argptr = 1;
uint32_t kernel_size = 0;
uint16_t checksum = 0;
uint8_t bugbootname[256];
if ( (argc != 3) )
{
fprintf(stderr, "usage: %s <kernel_image> <bugboot>\n",argv[0]);
exit(-1);
}
/* Get file args */
/* kernel image file */
if ((image_fd = open( argv[argptr] , 0)) < 0)
exit(-1);
argptr++;
int image_fd, bugboot_fd;
uint32_t kernel_size = 0;
uint16_t checksum = 0;
/* bugboot file */
if ( !strcmp( argv[argptr], "-" ) )
bugboot_fd = 1; /* stdout */
else
if ((bugboot_fd = creat( argv[argptr] , 0755)) < 0)
exit(-1);
else
strcpy(bugbootname, argv[argptr]);
argptr++;
if (argc != 3) {
fprintf(stderr, "usage: %s <kernel_image> <bugboot>\n",argv[0]);
exit(-1);
}
/* Set file position after ROM header block where zImage will be written */
lseek(bugboot_fd, HEADER_SIZE, SEEK_SET);
/* Get file args */
/* Copy kernel image into bugboot image */
kernel_size = copy_image(image_fd, bugboot_fd);
close(image_fd);
/* kernel image file */
if ((image_fd = open(argv[1] , 0)) < 0)
exit(-1);
/* Set file position to beginning where header/romboot will be written */
lseek(bugboot_fd, 0, SEEK_SET);
/* bugboot file */
if (!strcmp(argv[2], "-"))
bugboot_fd = 1; /* stdout */
else if ((bugboot_fd = creat(argv[2] , 0755)) < 0)
exit(-1);
/* Write out BUG header/romboot */
write_bugboot_header(bugboot_fd, kernel_size);
/* Set file position after ROM header block where zImage will be written */
lseek(bugboot_fd, HEADER_SIZE, SEEK_SET);
/* Close bugboot file */
close(bugboot_fd);
/* Copy kernel image into bugboot image */
kernel_size = copy_image(image_fd, bugboot_fd, &checksum);
/* Reopen it as read/write */
bugboot_fd = open(bugbootname, O_RDWR);
/* Set file position to beginning where header/romboot will be written */
lseek(bugboot_fd, 0, SEEK_SET);
/* Calculate checksum */
checksum = calc_checksum(bugboot_fd);
/* Write out BUG header/romboot */
write_bugboot_header(bugboot_fd, kernel_size, &checksum);
/* Write out the calculated checksum */
write(bugboot_fd, &checksum, 2);
/* Write out the calculated checksum */
lseek(bugboot_fd, 0, SEEK_END);
write(bugboot_fd, &checksum, 2);
return 0;
/* Close bugboot file */
close(bugboot_fd);
return 0;
}
arch/ppc/boot/utils/mkprep.c
View file @ ccaa36f7
This diff is collapsed.
arch/ppc/platforms/mpc8272ads_setup.c
View file @ ccaa36f7
......@@ -103,7 +103,7 @@ static struct fs_platform_info mpc82xx_enet_pdata[] = {
},
};
static void init_fcc1_ioports(void)
static void init_fcc1_ioports(struct fs_platform_info*)
{
struct io_port *io;
u32 tempval;
......@@ -144,7 +144,7 @@ static void init_fcc1_ioports(void)
iounmap(immap);
}
static void init_fcc2_ioports(void)
static void init_fcc2_ioports(struct fs_platform_info*)
{
cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
u32 *bcsr = ioremap(BCSR_ADDR+12, sizeof(u32));
......@@ -229,7 +229,7 @@ static void mpc8272ads_fixup_uart_pdata(struct platform_device *pdev,
}
}
static void init_scc1_uart_ioports(void)
static void init_scc1_uart_ioports(struct fs_uart_platform_info*)
{
cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
......@@ -246,7 +246,7 @@ static void init_scc1_uart_ioports(void)
iounmap(immap);
}
static void init_scc4_uart_ioports(void)
static void init_scc4_uart_ioports(struct fs_uart_platform_info*)
{
cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
......
arch/ppc/platforms/mpc866ads_setup.c
View file @ ccaa36f7
......@@ -137,7 +137,7 @@ void __init board_init(void)
iounmap(bcsr_io);
}
static void setup_fec1_ioports(void)
static void setup_fec1_ioports(struct fs_platform_info*)
{
immap_t *immap = (immap_t *) IMAP_ADDR;
......@@ -145,7 +145,7 @@ static void setup_fec1_ioports(void)
setbits16(&immap->im_ioport.iop_pddir, 0x1fff);
}
static void setup_scc1_ioports(void)
static void setup_scc1_ioports(struct fs_platform_info*)
{
immap_t *immap = (immap_t *) IMAP_ADDR;
unsigned *bcsr_io;
......@@ -194,7 +194,7 @@ static void setup_scc1_ioports(void)
}
static void setup_smc1_ioports(void)
static void setup_smc1_ioports(struct fs_uart_platform_info*)
{
immap_t *immap = (immap_t *) IMAP_ADDR;
unsigned *bcsr_io;
......@@ -216,7 +216,7 @@ static void setup_smc1_ioports(void)
}
static void setup_smc2_ioports(void)
static void setup_smc2_ioports(struct fs_uart_platform_info*)
{
immap_t *immap = (immap_t *) IMAP_ADDR;
unsigned *bcsr_io;
......
arch/ppc/platforms/mpc885ads_setup.c
View file @ ccaa36f7
......@@ -161,7 +161,7 @@ void __init board_init(void)
#endif
}
static void setup_fec1_ioports(void)
static void setup_fec1_ioports(struct fs_platform_info*)
{
immap_t *immap = (immap_t *) IMAP_ADDR;
......@@ -181,7 +181,7 @@ static void setup_fec1_ioports(void)
clrbits32(&immap->im_cpm.cp_cptr, 0x00000100);
}
static void setup_fec2_ioports(void)
static void setup_fec2_ioports(struct fs_platform_info*)
{
immap_t *immap = (immap_t *) IMAP_ADDR;
......@@ -193,7 +193,7 @@ static void setup_fec2_ioports(void)
clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
}
static void setup_scc3_ioports(void)
static void setup_scc3_ioports(struct fs_platform_info*)
{
immap_t *immap = (immap_t *) IMAP_ADDR;
unsigned *bcsr_io;
......@@ -315,7 +315,7 @@ static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev,
mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
}
static void setup_smc1_ioports(void)
static void setup_smc1_ioports(struct fs_uart_platform_info*)
{
immap_t *immap = (immap_t *) IMAP_ADDR;
unsigned *bcsr_io;
......@@ -335,7 +335,7 @@ static void setup_smc1_ioports(void)
clrbits16(&immap->im_cpm.cp_pbodr, iobits);
}
static void setup_smc2_ioports(void)
static void setup_smc2_ioports(struct fs_uart_platform_info*)
{
immap_t *immap = (immap_t *) IMAP_ADDR;
unsigned *bcsr_io;
......
drivers/char/hvc_iseries.c
View file @ ccaa36f7
......@@ -153,9 +153,7 @@ static int put_chars(uint32_t vtermno, const char *buf, int count)
spin_lock_irqsave(&consolelock, flags);
if (viochar_is_console(pi) && !viopath_isactive(pi->lp)) {
spin_lock_irqsave(&consoleloglock, flags);
HvCall_writeLogBuffer(buf, count);
spin_unlock_irqrestore(&consoleloglock, flags);
sent = count;
goto done;
}
......@@ -171,11 +169,8 @@ static int put_chars(uint32_t vtermno, const char *buf, int count)
len = (count > VIOCHAR_MAX_DATA) ? VIOCHAR_MAX_DATA : count;
if (viochar_is_console(pi)) {
spin_lock_irqsave(&consoleloglock, flags);
if (viochar_is_console(pi))
HvCall_writeLogBuffer(buf, len);
spin_unlock_irqrestore(&consoleloglock, flags);
}
init_data_event(viochar, pi->lp);
......
drivers/macintosh/via-pmu.c
View file @ ccaa36f7
......@@ -336,8 +336,10 @@ int __init find_via_pmu(void)
if (gaddr != OF_BAD_ADDR)
gpio_reg = ioremap(gaddr, 0x10);
}
if (gpio_reg == NULL)
if (gpio_reg == NULL) {
printk(KERN_ERR "via-pmu: Can't find GPIO reg !\n");
goto fail_gpio;
}
} else
pmu_kind = PMU_UNKNOWN;
......@@ -365,6 +367,9 @@ int __init find_via_pmu(void)
return 1;
fail:
of_node_put(vias);
iounmap(gpio_reg);
gpio_reg = NULL;
fail_gpio:
vias = NULL;
return 0;
}
......
drivers/net/fs_enet/fs_enet-main.c
View file @ ccaa36f7
......@@ -944,12 +944,13 @@ extern int fs_mii_connect(struct net_device *dev);
extern void fs_mii_disconnect(struct net_device *dev);
static struct net_device *fs_init_instance(struct device *dev,
const struct fs_platform_info *fpi)
struct fs_platform_info *fpi)
{
struct net_device *ndev = NULL;
struct fs_enet_private *fep = NULL;
int privsize, i, r, err = 0, registered = 0;
fpi->fs_no = fs_get_id(fpi);
/* guard */
if ((unsigned int)fpi->fs_no >= FS_MAX_INDEX)
return ERR_PTR(-EINVAL);
......@@ -971,7 +972,7 @@ static struct net_device *fs_init_instance(struct device *dev,
dev_set_drvdata(dev, ndev);
fep->fpi = fpi;
if (fpi->init_ioports)
fpi->init_ioports();
fpi->init_ioports((struct fs_platform_info *)fpi);
#ifdef CONFIG_FS_ENET_HAS_FEC
if (fs_get_fec_index(fpi->fs_no) >= 0)
......
drivers/pnp/isapnp/core.c
View file @ ccaa36f7
......@@ -1049,6 +1049,10 @@ static int __init isapnp_init(void)
printk(KERN_INFO "isapnp: ISA Plug & Play support disabled\n");
return 0;
}
#ifdef CONFIG_PPC_MERGE
if (check_legacy_ioport(_PIDXR) || check_legacy_ioport(_PNPWRP))
return -EINVAL;
#endif
#ifdef ISAPNP_REGION_OK
if (!request_region(_PIDXR, 1, "isapnp index")) {
printk(KERN_ERR "isapnp: Index Register 0x%x already used\n", _PIDXR);
......
drivers/serial/8250.c
View file @ ccaa36f7
......@@ -320,8 +320,8 @@ static unsigned int serial_in(struct uart_8250_port *up, int offset)
case UPIO_TSI:
if (offset == UART_IIR) {
tmp = readl((u32 *)(up->port.membase + UART_RX));
return (cpu_to_le32(tmp) >> 8) & 0xff;
tmp = readl(up->port.membase + (UART_IIR & ~3));
return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
} else
return readb(up->port.membase + offset);
......
drivers/serial/cpm_uart/cpm_uart_core.c
View file @ ccaa36f7
......@@ -46,6 +46,7 @@
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/delay.h>
#include <asm/fs_pd.h>
#if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
......@@ -1022,15 +1023,17 @@ int cpm_uart_drv_get_platform_data(struct platform_device *pdev, int is_con)
{
struct resource *r;
struct fs_uart_platform_info *pdata = pdev->dev.platform_data;
int idx = pdata->fs_no; /* It is UART_SMCx or UART_SCCx index */
int idx; /* It is UART_SMCx or UART_SCCx index */
struct uart_cpm_port *pinfo;
int line;
u32 mem, pram;
idx = pdata->fs_no = fs_uart_get_id(pdata);
line = cpm_uart_id2nr(idx);
if(line < 0) {
printk(KERN_ERR"%s(): port %d is not registered", __FUNCTION__, idx);
return -1;
return -EINVAL;
}
pinfo = (struct uart_cpm_port *) &cpm_uart_ports[idx];
......@@ -1044,11 +1047,11 @@ int cpm_uart_drv_get_platform_data(struct platform_device *pdev, int is_con)
if (!(r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs")))
return -EINVAL;
mem = r->start;
mem = (u32)ioremap(r->start, r->end - r->start + 1);
if (!(r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pram")))
return -EINVAL;
pram = r->start;
pram = (u32)ioremap(r->start, r->end - r->start + 1);
if(idx > fsid_smc2_uart) {
pinfo->sccp = (scc_t *)mem;
......@@ -1179,7 +1182,7 @@ static int __init cpm_uart_console_setup(struct console *co, char *options)
pdata = pdev->dev.platform_data;
if (pdata)
if (pdata->init_ioports)
pdata->init_ioports();
pdata->init_ioports(pdata);
cpm_uart_drv_get_platform_data(pdev, 1);
}
......@@ -1189,11 +1192,7 @@ static int __init cpm_uart_console_setup(struct console *co, char *options)
if (options) {
uart_parse_options(options, &baud, &parity, &bits, &flow);
} else {
bd_t *bd = (bd_t *) __res;
if (bd->bi_baudrate)
baud = bd->bi_baudrate;
else
if ((baud = uart_baudrate()) == -1)
baud = 9600;
}
......@@ -1266,13 +1265,14 @@ static int cpm_uart_drv_probe(struct device *dev)
}
pdata = pdev->dev.platform_data;
pr_debug("cpm_uart_drv_probe: Adding CPM UART %d\n", cpm_uart_id2nr(pdata->fs_no));
if ((ret = cpm_uart_drv_get_platform_data(pdev, 0)))
return ret;
pr_debug("cpm_uart_drv_probe: Adding CPM UART %d\n", cpm_uart_id2nr(pdata->fs_no));
if (pdata->init_ioports)
pdata->init_ioports();
pdata->init_ioports(pdata);
ret = uart_add_one_port(&cpm_reg, &cpm_uart_ports[pdata->fs_no].port);
......
drivers/serial/cpm_uart/cpm_uart_cpm2.c
View file @ ccaa36f7
......@@ -40,6 +40,7 @@
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/fs_pd.h>
#include <linux/serial_core.h>
#include <linux/kernel.h>
......@@ -50,8 +51,9 @@
void cpm_line_cr_cmd(int line, int cmd)
{
volatile cpm_cpm2_t *cp = cpmp;
ulong val;
volatile cpm_cpm2_t *cp = cpm2_map(im_cpm);
switch (line) {
case UART_SMC1:
......@@ -84,11 +86,14 @@ void cpm_line_cr_cmd(int line, int cmd)
}
cp->cp_cpcr = val;
while (cp->cp_cpcr & CPM_CR_FLG) ;
cpm2_unmap(cp);
}
void smc1_lineif(struct uart_cpm_port *pinfo)
{
volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
/* SMC1 is only on port D */
io->iop_ppard |= 0x00c00000;
......@@ -97,13 +102,17 @@ void smc1_lineif(struct uart_cpm_port *pinfo)
io->iop_psord &= ~0x00c00000;
/* Wire BRG1 to SMC1 */
cpm2_immr->im_cpmux.cmx_smr &= 0x0f;
cpmux->cmx_smr &= 0x0f;
pinfo->brg = 1;
cpm2_unmap(cpmux);
cpm2_unmap(io);
}
void smc2_lineif(struct uart_cpm_port *pinfo)
{
volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
/* SMC2 is only on port A */
io->iop_ppara |= 0x00c00000;
......@@ -112,13 +121,17 @@ void smc2_lineif(struct uart_cpm_port *pinfo)
io->iop_psora &= ~0x00c00000;
/* Wire BRG2 to SMC2 */
cpm2_immr->im_cpmux.cmx_smr &= 0xf0;
cpmux->cmx_smr &= 0xf0;
pinfo->brg = 2;
cpm2_unmap(cpmux);
cpm2_unmap(io);
}
void scc1_lineif(struct uart_cpm_port *pinfo)
{
volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
/* Use Port D for SCC1 instead of other functions. */
io->iop_ppard |= 0x00000003;
......@@ -128,9 +141,12 @@ void scc1_lineif(struct uart_cpm_port *pinfo)
io->iop_pdird |= 0x00000002; /* Tx */
/* Wire BRG1 to SCC1 */
cpm2_immr->im_cpmux.cmx_scr &= 0x00ffffff;
cpm2_immr->im_cpmux.cmx_scr |= 0x00000000;
cpmux->cmx_scr &= 0x00ffffff;
cpmux->cmx_scr |= 0x00000000;
pinfo->brg = 1;
cpm2_unmap(cpmux);
cpm2_unmap(io);
}
void scc2_lineif(struct uart_cpm_port *pinfo)
......@@ -143,43 +159,57 @@ void scc2_lineif(struct uart_cpm_port *pinfo)
* be supported in a sane fashion.
*/
#ifndef CONFIG_STX_GP3
volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
io->iop_pparb |= 0x008b0000;
io->iop_pdirb |= 0x00880000;
io->iop_psorb |= 0x00880000;
io->iop_pdirb &= ~0x00030000;
io->iop_psorb &= ~0x00030000;
#endif
cpm2_immr->im_cpmux.cmx_scr &= 0xff00ffff;
cpm2_immr->im_cpmux.cmx_scr |= 0x00090000;
cpmux->cmx_scr &= 0xff00ffff;
cpmux->cmx_scr |= 0x00090000;
pinfo->brg = 2;
cpm2_unmap(cpmux);
cpm2_unmap(io);
}
void scc3_lineif(struct uart_cpm_port *pinfo)
{
volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
io->iop_pparb |= 0x008b0000;
io->iop_pdirb |= 0x00880000;
io->iop_psorb |= 0x00880000;
io->iop_pdirb &= ~0x00030000;
io->iop_psorb &= ~0x00030000;
cpm2_immr->im_cpmux.cmx_scr &= 0xffff00ff;
cpm2_immr->im_cpmux.cmx_scr |= 0x00001200;
cpmux->cmx_scr &= 0xffff00ff;
cpmux->cmx_scr |= 0x00001200;
pinfo->brg = 3;
cpm2_unmap(cpmux);
cpm2_unmap(io);
}
void scc4_lineif(struct uart_cpm_port *pinfo)
{
volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
volatile iop_cpm2_t *io = cpm2_map(im_ioport);
volatile cpmux_t *cpmux = cpm2_map(im_cpmux);
io->iop_ppard |= 0x00000600;
io->iop_psord &= ~0x00000600; /* Tx/Rx */
io->iop_pdird &= ~0x00000200; /* Rx */
io->iop_pdird |= 0x00000400; /* Tx */
cpm2_immr->im_cpmux.cmx_scr &= 0xffffff00;
cpm2_immr->im_cpmux.cmx_scr |= 0x0000001b;
cpmux->cmx_scr &= 0xffffff00;
cpmux->cmx_scr |= 0x0000001b;
pinfo->brg = 4;
cpm2_unmap(cpmux);
cpm2_unmap(io);
}
/*
......@@ -254,88 +284,103 @@ void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
/* Setup any dynamic params in the uart desc */
int cpm_uart_init_portdesc(void)
{
#if defined(CONFIG_SERIAL_CPM_SMC1) || defined(CONFIG_SERIAL_CPM_SMC2)
u32 addr;
#endif
pr_debug("CPM uart[-]:init portdesc\n");
cpm_uart_nr = 0;
#ifdef CONFIG_SERIAL_CPM_SMC1
cpm_uart_ports[UART_SMC1].smcp = (smc_t *) & cpm2_immr->im_smc[0];
cpm_uart_ports[UART_SMC1].smcup =
(smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC1];
*(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC1_BASE]) = PROFF_SMC1;
cpm_uart_ports[UART_SMC1].smcp = (smc_t *) cpm2_map(im_smc[0]);
cpm_uart_ports[UART_SMC1].port.mapbase =
(unsigned long)&cpm2_immr->im_smc[0];
(unsigned long)cpm_uart_ports[UART_SMC1].smcp;
cpm_uart_ports[UART_SMC1].smcup =
(smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC1], PROFF_SMC_SIZE);
addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC1_BASE], 2);
*addr = PROFF_SMC1;
cpm2_unmap(addr);
cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
cpm_uart_ports[UART_SMC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
#endif
#ifdef CONFIG_SERIAL_CPM_SMC2
cpm_uart_ports[UART_SMC2].smcp = (smc_t *) & cpm2_immr->im_smc[1];
cpm_uart_ports[UART_SMC2].smcup =
(smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC2];
*(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC2_BASE]) = PROFF_SMC2;
cpm_uart_ports[UART_SMC2].smcp = (smc_t *) cpm2_map(im_smc[1]);
cpm_uart_ports[UART_SMC2].port.mapbase =
(unsigned long)&cpm2_immr->im_smc[1];
(unsigned long)cpm_uart_ports[UART_SMC2].smcp;
cpm_uart_ports[UART_SMC2].smcup =
(smc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SMC2], PROFF_SMC_SIZE);
addr = (u16 *)cpm2_map_size(im_dprambase[PROFF_SMC2_BASE], 2);
*addr = PROFF_SMC2;
cpm2_unmap(addr);
cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
cpm_uart_ports[UART_SMC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
#endif
#ifdef CONFIG_SERIAL_CPM_SCC1
cpm_uart_ports[UART_SCC1].sccp = (scc_t *) & cpm2_immr->im_scc[0];
cpm_uart_ports[UART_SCC1].sccup =
(scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC1];
cpm_uart_ports[UART_SCC1].sccp = (scc_t *) cpm2_map(im_scc[0]);
cpm_uart_ports[UART_SCC1].port.mapbase =
(unsigned long)&cpm2_immr->im_scc[0];
(unsigned long)cpm_uart_ports[UART_SCC1].sccp;
cpm_uart_ports[UART_SCC1].sccup =
(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC1], PROFF_SCC_SIZE);
cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
~(UART_SCCM_TX | UART_SCCM_RX);
cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
cpm_uart_ports[UART_SCC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
#endif
#ifdef CONFIG_SERIAL_CPM_SCC2
cpm_uart_ports[UART_SCC2].sccp = (scc_t *) & cpm2_immr->im_scc[1];
cpm_uart_ports[UART_SCC2].sccup =
(scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC2];
cpm_uart_ports[UART_SCC2].sccp = (scc_t *) cpm2_map(im_scc[1]);
cpm_uart_ports[UART_SCC2].port.mapbase =
(unsigned long)&cpm2_immr->im_scc[1];
(unsigned long)cpm_uart_ports[UART_SCC2].sccp;
cpm_uart_ports[UART_SCC2].sccup =
(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC2], PROFF_SCC_SIZE);
cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
~(UART_SCCM_TX | UART_SCCM_RX);
cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
cpm_uart_ports[UART_SCC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
#endif
#ifdef CONFIG_SERIAL_CPM_SCC3
cpm_uart_ports[UART_SCC3].sccp = (scc_t *) & cpm2_immr->im_scc[2];
cpm_uart_ports[UART_SCC3].sccup =
(scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC3];
cpm_uart_ports[UART_SCC3].sccp = (scc_t *) cpm2_map(im_scc[2]);
cpm_uart_ports[UART_SCC3].port.mapbase =
(unsigned long)&cpm2_immr->im_scc[2];
(unsigned long)cpm_uart_ports[UART_SCC3].sccp;
cpm_uart_ports[UART_SCC3].sccup =
(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC3], PROFF_SCC_SIZE);
cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
~(UART_SCCM_TX | UART_SCCM_RX);
cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
cpm_uart_ports[UART_SCC3].port.uartclk = (((bd_t *) __res)->bi_intfreq);
cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
#endif
#ifdef CONFIG_SERIAL_CPM_SCC4
cpm_uart_ports[UART_SCC4].sccp = (scc_t *) & cpm2_immr->im_scc[3];
cpm_uart_ports[UART_SCC4].sccup =
(scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC4];
cpm_uart_ports[UART_SCC4].sccp = (scc_t *) cpm2_map(im_scc[3]);
cpm_uart_ports[UART_SCC4].port.mapbase =
(unsigned long)&cpm2_immr->im_scc[3];
(unsigned long)cpm_uart_ports[UART_SCC4].sccp;
cpm_uart_ports[UART_SCC4].sccup =
(scc_uart_t *) cpm2_map_size(im_dprambase[PROFF_SCC4], PROFF_SCC_SIZE);
cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
~(UART_SCCM_TX | UART_SCCM_RX);
cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
cpm_uart_ports[UART_SCC4].port.uartclk = (((bd_t *) __res)->bi_intfreq);
cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
#endif
......
drivers/serial/cpm_uart/cpm_uart_cpm2.h
View file @ ccaa36f7
......@@ -40,6 +40,6 @@ static inline void cpm_set_smc_fcr(volatile smc_uart_t * up)
up->smc_tfcr = CPMFCR_GBL | CPMFCR_EB;
}
#define DPRAM_BASE ((unsigned char *)&cpm2_immr->im_dprambase[0])
#define DPRAM_BASE ((unsigned char *)cpm_dpram_addr(0))
#endif
include/asm-powerpc/fs_pd.h 0 → 100644
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/*
* Platform information definitions.
*
* 2006 (c) MontaVista Software, Inc.
* Vitaly Bordug <vbordug@ru.mvista.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef FS_PD_H
#define FS_PD_H
#include <asm/cpm2.h>
#include <sysdev/fsl_soc.h>
#include <asm/time.h>
static inline int uart_baudrate(void)
{
return get_baudrate();
}
static inline int uart_clock(void)
{
return ppc_proc_freq;
}
#define cpm2_map(member) \
({ \
u32 offset = offsetof(cpm2_map_t, member); \
void *addr = ioremap (CPM_MAP_ADDR + offset, \
sizeof( ((cpm2_map_t*)0)->member)); \
addr; \
})
#define cpm2_map_size(member, size) \
({ \
u32 offset = offsetof(cpm2_map_t, member); \
void *addr = ioremap (CPM_MAP_ADDR + offset, size); \
addr; \
})
#define cpm2_unmap(addr) iounmap(addr)
#endif
include/asm-powerpc/mpc85xx.h 0 → 100644
View file @ ccaa36f7
/*
* include/asm-powerpc/mpc85xx.h
*
* MPC85xx definitions
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2004 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifdef __KERNEL__
#ifndef __ASM_MPC85xx_H__
#define __ASM_MPC85xx_H__
#include <asm/mmu.h>
#ifdef CONFIG_85xx
#if defined(CONFIG_MPC8540_ADS) || defined(CONFIG_MPC8560_ADS)
#include <platforms/85xx/mpc85xx_ads.h>
#endif
#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
#include <platforms/85xx/mpc8555_cds.h>
#endif
#ifdef CONFIG_MPC85xx_CDS
#include <platforms/85xx/mpc85xx_cds.h>
#endif
#define _IO_BASE isa_io_base
#define _ISA_MEM_BASE isa_mem_base
#ifdef CONFIG_PCI
#define PCI_DRAM_OFFSET pci_dram_offset
#else
#define PCI_DRAM_OFFSET 0
#endif
/* Let modules/drivers get at CCSRBAR */
extern phys_addr_t get_ccsrbar(void);
#ifdef MODULE
#define CCSRBAR get_ccsrbar()
#else
#define CCSRBAR BOARD_CCSRBAR
#endif
#endif /* CONFIG_85xx */
#endif /* __ASM_MPC85xx_H__ */
#endif /* __KERNEL__ */
include/asm-powerpc/time.h
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include/asm-ppc/cpm2.h
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include/asm-ppc/fs_pd.h 0 → 100644
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include/asm-ppc/rheap.h
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include/linux/fs_enet_pd.h
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include/linux/fs_uart_pd.h
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