Skip to content

L
linux-davinci
Commit ca9ce1a6 authored by Ramesh Gupta's avatar Ramesh Gupta Committed by Hari Kanigeri
Browse files
Options

Bridge changes cleanup prcm Bridge changes cleanup prcm 

Signed-off-by: default avatarRamesh Gupta G <grgupta@ti.com>
parent c3d8ab66
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 522 additions and 643 deletions
arch/arm/plat-omap/include/dspbridge/host_os.h
View file @ ca9ce1a6
......@@ -91,5 +91,6 @@ static inline void dspbridge_reserve_sdram(void) {}
#endif
extern unsigned long dspbridge_get_mempool_base(void);
#endif
drivers/dsp/bridge/hw/PRCMAccInt.h
View file @ ca9ce1a6
This diff is collapsed.
drivers/dsp/bridge/hw/PRCMRegAcM.h
View file @ ca9ce1a6
This diff is collapsed.
drivers/dsp/bridge/hw/hw_prcm.c
View file @ ca9ce1a6
......@@ -29,11 +29,11 @@
#include <hw_defs.h>
#include <hw_prcm.h>
#ifdef OMAP_3430
static HW_STATUS HW_RST_WriteVal(const void __iomem *baseAddress,
enum HW_RstModule_t r,
enum HW_SetClear_t val);
enum HW_RstModule_t r,
enum HW_SetClear_t val);
HW_STATUS HW_RST_Reset(const void __iomem *baseAddress, enum HW_RstModule_t r)
{
......@@ -46,28 +46,38 @@ HW_STATUS HW_RST_UnReset(const void __iomem *baseAddress, enum HW_RstModule_t r)
}
static HW_STATUS HW_RST_WriteVal(const void __iomem *baseAddress,
enum HW_RstModule_t r,
enum HW_SetClear_t val)
enum HW_RstModule_t r,
enum HW_SetClear_t val)
{
HW_STATUS status = RET_OK;
switch (r) {
#ifdef OMAP44XX
case HW_RST1_TESLA:
PRM_TESLA_RSTCTRL_RST1_Write32(baseAddress, val);
break;
case HW_RST2_TESLA:
PRM_TESLA_RSTCTRL_RST2_Write32(baseAddress, val);
break;
#else
case HW_RST1_IVA2:
PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress, val);
break;
PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress, val);
break;
case HW_RST2_IVA2:
PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress, val);
break;
PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress, val);
break;
case HW_RST3_IVA2:
PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress, val);
break;
PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress, val);
break;
#endif
default:
status = RET_FAIL;
break;
status = RET_FAIL;
break;
}
return status;
}
#ifdef OMAP_3430
HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
enum HW_PwrModule_t p, enum HW_PwrState_t *value)
{
......@@ -83,7 +93,6 @@ HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
(baseAddress);
} while (temp);
temp = PRCMPM_PWSTST_IVA2ReadRegister32(baseAddress);
*value = PRCMPM_PWSTST_IVA2PowerStateStGet32(temp);
break;
......@@ -147,13 +156,18 @@ HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const void __iomem *baseAddress,
return status;
}
#endif
HW_STATUS HW_RSTST_RegGet(const void __iomem *baseAddress,
enum HW_RstModule_t m, u32 *value)
{
HW_STATUS status = RET_OK;
#ifdef OMAP44XX
*value = PRM_TESLA_RSTSTReadRegister32(baseAddress);
#else
*value = PRCMRM_RSTST_DSPReadRegister32(baseAddress);
#endif
return status;
}
......@@ -162,21 +176,21 @@ HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
enum HW_RstModule_t m, u32 *value)
{
HW_STATUS status = RET_OK;
#ifdef OMAP44XX
*value = PRM_TESLA_RSTCTRLReadRegister32(baseAddress);
#else
*value = PRCMRM_RSTCTRL_DSPReadRegister32(baseAddress);
#endif
return status;
}
#else
#ifdef OMAP44XX
static HW_STATUS HW_CLK_WriteVal (const u32 baseAddress, enum HW_ClkModule_t c, enum HW_SetClear_t val);
static HW_STATUS HW_CLK_AutoIdleWriteVal (const u32 baseAddress, enum HW_ClkModule_t c, enum HW_SetClear_t val);
static HW_STATUS HW_RST_WriteVal (const u32 baseAddress, enum HW_RstModule_t r, enum HW_SetClear_t val);
/* ============================================================================
* EXPORTED FUNCTIONS
* =============================================================================
*/
HW_STATUS HW_CLK_Enable(const u32 baseAddress, enum HW_ClkModule_t c)
{
......@@ -196,7 +210,6 @@ static HW_STATUS HW_CLK_WriteVal (const u32 baseAddress, enum HW_ClkModule_t c,
if (val == HW_SET)
val_clk = 0x2;
switch (c) {
case HW_CLK_TESLA:
CM_TESLA_TESLA_CLKCTRLWriteRegister32(baseAddress, val);
......@@ -246,6 +259,33 @@ static HW_STATUS HW_CLK_WriteVal (const u32 baseAddress, enum HW_ClkModule_t c,
case HW_CLK_DMTIMER11:
CM_L4PEREN_DMTIMER11Write32(baseAddress, val_clk);
break;
default:
status = RET_FAIL;
break;
}
return status;
}
HW_STATUS HW_PWRSTCTRL_RegGet(const u32 baseAddress, u32 *value)
{
HW_STATUS status = RET_OK;
*value = PRM_TESLA_PWRSTCTRLReadRegister32(baseAddress);
return status;
}
HW_STATUS HW_PWR_PowerStateGet(const u32 baseAddress,
enum HW_PwrModule_t p, enum HW_PwrState_t *value)
{
HW_STATUS status = RET_OK;
switch (p) {
case HW_PWR_DOMAIN_TESLA:
*value = (enum HW_PwrState_t)PRM_TESLA_PWRSTSTGet32(baseAddress);
break;
default:
status = RET_FAIL;
......@@ -255,8 +295,83 @@ static HW_STATUS HW_CLK_WriteVal (const u32 baseAddress, enum HW_ClkModule_t c,
return status;
}
HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
enum HW_PwrModule_t p, enum HW_PwrState_t value)
{
HW_STATUS status = RET_OK;
switch (p) {
case HW_PWR_DOMAIN_TESLA:
switch (value) {
case HW_PWR_STATE_ON:
PRM_TESLA_PWRSTCTRLWriteON32(baseAddress);
break;
case HW_PWR_STATE_INACT:
PRM_TESLA_PWRSTCTRLWriteINACTIVE32(baseAddress);
break;
case HW_PWR_STATE_RET:
PRM_TESLA_PWRSTCTRLWriteRET32(baseAddress);
break;
case HW_PWR_STATE_OFF:
PRM_TESLA_PWRSTCTRLWriteOFF32(baseAddress);
break;
default:
status = RET_FAIL;
break;
}
break;
case HW_PWR_DOMAIN_CORE:
switch (value) {
case HW_PWR_STATE_ON:
case HW_PWR_STATE_INACT:
case HW_PWR_STATE_RET:
case HW_PWR_STATE_OFF:
PRM_CORE_PWRSTCTRLWrite32(baseAddress, value);
break;
default:
status = RET_FAIL;
break;
}
break;
default:
status = RET_FAIL;
break;
}
return status;
}
HW_STATUS HW_PWR_ForceStateSet(const u32 baseAddress, enum HW_PwrModule_t p,
enum HW_TransitionState_t value)
{
HW_STATUS status = RET_OK;
switch (p) {
case HW_PWR_DOMAIN_TESLA:
CM_CLKSTCTRL_TESLAWriteRegister32(baseAddress, value);
break;
case HW_PWR_DOMAIN_ABE:
CM_CLKSTCTRL_ABEWriteRegister32(baseAddress, value);
break;
case HW_PWR_DOMAIN_L4PER:
CM_CLKSTCTRL_L4PERWriteRegister32(baseAddress, value);
break;
default:
status = RET_FAIL;
break;
}
return status;
}
#endif
#if 0
HW_STATUS HW_CLK_AutoIdleEnable(const u32 baseAddress, enum HW_ClkModule_t c)
{
return HW_CLK_AutoIdleWriteVal(baseAddress, c, HW_SET);
......@@ -321,6 +436,7 @@ HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress, u32 *value)
return status;
}
static HW_STATUS HW_RST_WriteVal(const u32 baseAddress, enum HW_RstModule_t p,
enum HW_SetClear_t value)
{
......@@ -342,16 +458,18 @@ static HW_STATUS HW_RST_WriteVal(const u32 baseAddress, enum HW_RstModule_t p,
return status;
}
HW_STATUS HW_RSTST_RegGet (const u32 baseAddress, u32 *value)
{
HW_STATUS status = RET_OK;
*value = PRM_TESLA_RSTSTReadRegister32(baseAddress);
return status;
}
HW_STATUS HW_RSTST_RegClear (const u32 baseAddress)
{
HW_STATUS status = RET_OK;
......@@ -362,77 +480,7 @@ HW_STATUS HW_RSTST_RegClear (const u32 baseAddress)
}
HW_STATUS HW_PWRSTCTRL_RegGet(const u32 baseAddress, u32 *value)
{
HW_STATUS status = RET_OK;
*value = PRM_TESLA_PWRSTCTRLReadRegister32(baseAddress);
return status;
}
HW_STATUS HW_PWR_PowerStateGet(const u32 baseAddress,
enum HW_PwrModule_t p, enum HW_PwrState_t *value)
{
HW_STATUS status = RET_OK;
switch (p) {
case HW_PWR_DOMAIN_TESLA:
*value = (enum HW_PwrState_t)PRM_TESLA_PWRSTSTGet32(baseAddress);
break;
default:
status = RET_FAIL;
break;
}
return status;
}
HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
enum HW_PwrModule_t p, enum HW_PwrState_t value)
{
HW_STATUS status = RET_OK;
switch (p) {
case HW_PWR_DOMAIN_TESLA:
switch (value) {
case HW_PWR_STATE_ON:
PRM_TESLA_PWRSTCTRLWriteON32(baseAddress);
break;
case HW_PWR_STATE_INACT:
PRM_TESLA_PWRSTCTRLWriteINACTIVE32(baseAddress);
break;
case HW_PWR_STATE_RET:
PRM_TESLA_PWRSTCTRLWriteRET32(baseAddress);
break;
case HW_PWR_STATE_OFF:
PRM_TESLA_PWRSTCTRLWriteOFF32(baseAddress);
break;
default:
status = RET_FAIL;
break;
}
break;
case HW_PWR_DOMAIN_CORE:
switch (value) {
case HW_PWR_STATE_ON:
case HW_PWR_STATE_INACT:
case HW_PWR_STATE_RET:
case HW_PWR_STATE_OFF:
PRM_CORE_PWRSTCTRLWrite32(baseAddress, value);
break;
default:
status = RET_FAIL;
break;
}
break;
default:
status = RET_FAIL;
break;
}
return status;
}
HW_STATUS HW_PWR_RetentionStateSet(const u32 baseAddress,
......@@ -467,6 +515,7 @@ HW_STATUS HW_PWR_RetentionStateSet(const u32 baseAddress,
}
HW_STATUS HW_PWRST_RegGet(const u32 baseAddress, enum HW_PwrModule_t p, u32 *value)
{
HW_STATUS status = RET_OK;
......@@ -492,6 +541,7 @@ HW_STATUS HW_PWR_WkupDependency_RegGet(const u32 baseAddress, u32 *value)
return status;
}
HW_STATUS HW_PWR_WkupDependencySet(const u32 baseAddress, enum HW_PwrModule_t p,
enum HW_WeakUpDep_t src, enum HW_SetClear_t value)
{
......@@ -519,28 +569,7 @@ HW_STATUS HW_PWR_WkupDependencySet(const u32 baseAddress, enum HW_PwrModule_t p,
return status;
}
HW_STATUS HW_PWR_ForceStateSet(const u32 baseAddress, enum HW_PwrModule_t p,
enum HW_PWR_TransState_t value)
{
HW_STATUS status = RET_OK;
switch (p) {
case HW_PWR_DOMAIN_TESLA:
CM_CLKSTCTRL_TESLAWriteRegister32(baseAddress, value);
break;
case HW_PWR_DOMAIN_ABE:
CM_CLKSTCTRL_ABEWriteRegister32(baseAddress, value);
break;
case HW_PWR_DOMAIN_L4PER:
CM_CLKSTCTRL_L4PERWriteRegister32(baseAddress, value);
break;
default:
status = RET_FAIL;
break;
}
return status;
}
HW_STATUS HW_TESLA_CONTEXT_RegGet(const u32 baseAddress, u32 *value)
......@@ -562,6 +591,7 @@ HW_STATUS HW_TESLA_CONTEXT_ClrSet(const u32 baseAddress)
}
HW_STATUS HW_ALWON_CONTEXT_RegGet(const u32 baseAddress, u32 *value)
{
HW_STATUS status = RET_OK;
......@@ -572,6 +602,7 @@ HW_STATUS HW_ALWON_CONTEXT_RegGet(const u32 baseAddress, u32 *value)
}
HW_STATUS HW_IVA_DVFSSet(const u32 baseAddress, enum HW_IvaDVFS_t src, u32 value)
{
HW_STATUS status = RET_OK;
......
drivers/dsp/bridge/hw/hw_prcm.h
View file @ ca9ce1a6
This diff is collapsed.
drivers/dsp/bridge/wmd/io_sm.c
View file @ ca9ce1a6
......@@ -220,17 +220,17 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
struct CFG_HOSTRES hostRes;
struct CFG_DEVNODE *hDevNode;
struct CHNL_MGR *hChnlMgr;
static int ref_count;
static int ref_count;
u32 devType;
struct notify_config ntfy_config;
struct notify_tesladrv_config tesla_cfg;
struct notify_tesladrv_params params;
u32 mem_va;
u32 mem_pa;
char driverName[32] = "NOTIFYMBXDRV";
int ntfystatus;
irq_handler = (void *) IO_ISR;
struct notify_config ntfy_config;
struct notify_tesladrv_config tesla_cfg;
struct notify_tesladrv_params params;
u32 mem_va;
u32 mem_pa;
char driverName[32] = "NOTIFYMBXDRV";
int ntfystatus;
irq_handler = (void *) IO_ISR;
/* Check DBC requirements: */
......@@ -256,16 +256,16 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
if (DSP_FAILED(status))
goto func_cont;
/*
* Create a Single Threaded Work Queue
*/
/*
* Create a Single Threaded Work Queue
*/
if (ref_count == 0)
bridge_workqueue = create_workqueue("bridge_work-queue");
if (ref_count == 0)
bridge_workqueue = create_workqueue("bridge_work-queue");
if (bridge_workqueue <= 0)
DBG_Trace(DBG_LEVEL1, "Workque Create"
" failed 0x%d \n", bridge_workqueue);
if (bridge_workqueue <= 0)
DBG_Trace(DBG_LEVEL1, "Workque Create"
" failed 0x%d \n", bridge_workqueue);
/* Allocate IO manager object: */
......@@ -274,14 +274,14 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
status = DSP_EMEMORY;
goto func_cont;
}
/*Intializing Work Element*/
if (ref_count == 0) {
INIT_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM);
ref_count = 1;
} else
PREPARE_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM);
/* Initialize CHNL_MGR object: */
/*Intializing Work Element*/
if (ref_count == 0) {
INIT_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM);
ref_count = 1;
} else
PREPARE_WORK(&pIOMgr->io_workq, (void *)IO_DispatchPM);
/* Initialize CHNL_MGR object:*/
#ifndef DSP_TRACEBUF_DISABLED
pIOMgr->pMsg = NULL;
#endif
......@@ -301,50 +301,55 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
pIOMgr->iQuePowerTail = 0;
}
notify_get_config(&ntfy_config);
ntfystatus = notify_setup(&ntfy_config);
if (NOTIFY_FAILED(ntfystatus)) {
DBG_Trace(DBG_LEVEL7, "Failed notify_setup ntfystatus 0x%x \n",
ntfystatus);
} else
printk("%s:%d:PASS\n",__func__,__LINE__);
notify_get_config(&ntfy_config);
ntfystatus = notify_setup(&ntfy_config);
notify_tesladrv_getconfig(&tesla_cfg);
ntfystatus = notify_tesladrv_setup(&tesla_cfg);
if (ntfystatus != NOTIFY_SUCCESS) {
pr_err("Failed notify_setup ntfystatus\n");
goto func_cont;
}
notify_tesladrv_params_init(NULL, &params);
notify_tesladrv_getconfig(&tesla_cfg);
mem_va = dma_alloc_coherent(NULL, 0x4000, &mem_pa,GFP_ATOMIC);
if (mem_va == NULL)
pr_err("Memory allocation for communication failed\n");
params.num_events = 32;
params.num_reserved_events = 0;
params.send_event_poll_count = (int) -1;
params.recv_int_id = 26;
params.send_int_id = 55;
params.shared_addr_size = 0x4000;
params.shared_addr = mem_va;
params.remote_proc_id = 0;
ntfystatus = notify_tesladrv_setup(&tesla_cfg);
handle = notify_tesladrv_create(driverName,&params);
if (NOTIFY_FAILED(ntfystatus)) {
DBG_Trace(DBG_LEVEL7, "Failed notify_get_driver_handle ntfystatus 0x%x \n",
ntfystatus);
}
if (ntfystatus != 0) {
pr_err("Failed notify_tesladrv_setup\n");
goto func_cont;
}
eventNo = ((NOTIFY_SYSTEM_KEY<<16)|NOTIFY_TESLA_EVENTNUMBER);
notify_tesladrv_params_init(NULL, &params);
ntfystatus = notify_register_event(handle, /*PROC_TESLA*/0, eventNo,(void*)IO_ISR, NULL);
mem_va = dma_alloc_coherent(NULL, 0x4000, &mem_pa, GFP_ATOMIC);
if (mem_va == NULL)
pr_err("Memory allocation for communication failed\n");
params.num_events = 32;
params.num_reserved_events = 0;
params.send_event_poll_count = (int) -1;
params.recv_int_id = 26;
params.send_int_id = 55;
params.shared_addr_size = 0x4000;
params.shared_addr = mem_va;
params.remote_proc_id = 0;
handle = notify_tesladrv_create(driverName, &params);
if (handle == NULL) {
pr_err("Failed notify_tesladrv_create\n");
goto func_cont;
}
if (NOTIFY_FAILED(ntfystatus)) {
DBG_Trace(DBG_LEVEL7, "Failed notify_register_event ntfystatus 0x%x \n",
ntfystatus);
}
eventNo = ((NOTIFY_SYSTEM_KEY<<16)|NOTIFY_TESLA_EVENTNUMBER);
notify_disable_event(handle, 0, eventNo);
ntfystatus = notify_register_event(handle, /*PROC_TESLA*/0,
eventNo, (void *)IO_ISR, NULL);
if (ntfystatus != NOTIFY_SUCCESS) {
pr_err("Failed notify_register_event\n");
goto func_cont;
}
notify_disable_event(handle, 0, eventNo);
if (DSP_SUCCEEDED(status)) {
status = CFG_GetHostResources((struct CFG_DEVNODE *)
......@@ -360,19 +365,19 @@ DSP_STATUS WMD_IO_Create(OUT struct IO_MGR **phIOMgr,
IO_DisableInterrupt(hWmdContext);
if (devType == DSP_UNIT) {
/* Plug the channel ISR:. */
if ((request_irq(INT_MAIL_MPU_IRQ, IO_ISR, 0,
"DspBridge\tmailbox", (void *)pIOMgr)) == 0)
status = DSP_SOK;
else
status = DSP_EFAIL;
if ((request_irq(INT_MAIL_MPU_IRQ, IO_ISR, 0,
"DspBridge\tmailbox", (void *)pIOMgr)) == 0)
status = DSP_SOK;
else
status = DSP_EFAIL;
}
#endif
if (DSP_SUCCEEDED(status))
DBG_Trace(DBG_LEVEL1, "ISR_IRQ Object 0x%x \n",
pIOMgr);
else
status = CHNL_E_ISR;
} else
if (DSP_SUCCEEDED(status))
DBG_Trace(DBG_LEVEL1, "ISR_IRQ Object 0x%x \n",
pIOMgr);
else
status = CHNL_E_ISR;
} else
status = CHNL_E_ISR;
func_cont:
if (DSP_FAILED(status)) {
......@@ -395,23 +400,24 @@ func_cont:
DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr)
{
DSP_STATUS status = DSP_SOK;
u32 notify_status;
#ifdef OMAP44XX
status = notify_tesladrv_delete(&handle);
status = notify_tesladrv_destroy();
status = notify_destroy();
notify_status = notify_tesladrv_delete(&handle);
notify_status = notify_tesladrv_destroy();
notify_status = notify_destroy();
#else
struct WMD_DEV_CONTEXT *hWmdContext;
if (MEM_IsValidHandle(hIOMgr, IO_MGRSIGNATURE)) {
/* Unplug IRQ: */
/* Disable interrupts from the board: */
if (DSP_SUCCEEDED(DEV_GetWMDContext(hIOMgr->hDevObject,
&hWmdContext)))
DBC_Assert(hWmdContext);
(void)CHNLSM_DisableInterrupt(hWmdContext);
destroy_workqueue(bridge_workqueue);
/* Linux function to uninstall ISR */
free_irq(INT_MAIL_MPU_IRQ, (void *)hIOMgr);
(void)DPC_Destroy(hIOMgr->hDPC);
/* Disable interrupts from the board: */
if (DSP_SUCCEEDED(DEV_GetWMDContext(hIOMgr->hDevObject,
&hWmdContext)))
DBC_Assert(hWmdContext);
(void)CHNLSM_DisableInterrupt(hWmdContext);
destroy_workqueue(bridge_workqueue);
/* uninstall ISR */
free_irq(INT_MAIL_MPU_IRQ, (void *)hIOMgr);
(void)DPC_Destroy(hIOMgr->hDPC);
#ifndef DSP_TRACEBUF_DISABLED
if (hIOMgr->pMsg)
MEM_Free(hIOMgr->pMsg);
......@@ -419,7 +425,7 @@ DSP_STATUS WMD_IO_Destroy(struct IO_MGR *hIOMgr)
SYNC_DeleteCS(hIOMgr->hCSObj); /* Leak Fix. */
/* Free this IO manager object: */
MEM_FreeObject(hIOMgr);
} else
} else
status = DSP_EHANDLE;
#endif
return status;
......@@ -626,7 +632,7 @@ func_cont1:
"numBytes %x\n", allBits, paCurr, vaCurr, numBytes);
for (i = 0; i < 4; i++) {
if ((numBytes >= pgSize[i]) && ((allBits &
(pgSize[i] - 1)) == 0)) {
(pgSize[i] - 1)) == 0)) {
status = hIOMgr->pIntfFxns->pfnBrdMemMap
(hIOMgr->hWmdContext, paCurr, vaCurr,
pgSize[i], mapAttrs);
......
drivers/dsp/bridge/wmd/tiomap3430.c
View file @ ca9ce1a6
......@@ -326,21 +326,19 @@ static DSP_STATUS WMD_BRD_Monitor(struct WMD_DEV_CONTEXT *hDevContext)
goto error_return;
#ifdef OMAP44XX
printk("Disabling Clocks... and resources.dwCm1Base = 0x%x \n resources.dwCm2Base= 0x%x\n"
printk("Disabling Clocks... and resources.dwCm1Base = 0x%x \n resources.dwCm2Base= 0x%x\n"
"resources.dwPrmBase = 0x%x", resources.dwCm1Base, resources.dwCm2Base, resources.dwPrmBase);
HW_CLK_Disable (resources.dwCm1Base, HW_CLK_TESLA) ;
printk("Resetting DSP...");
HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);
printk("Enabling Clocks...");
HW_CLK_Enable (resources.dwCm1Base, HW_CLK_TESLA) ;
HW_CLK_Disable (resources.dwCm1Base, HW_CLK_TESLA) ;
printk("Resetting DSP...");
HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);
printk("Enabling Clocks...");
HW_CLK_Enable (resources.dwCm1Base, HW_CLK_TESLA) ;
HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);/*TODO check if it is correct*/
HW_RST_Reset(resources.dwPrmBase, HW_RST2_TESLA);/*Just to ensure that the RST's are enabled*/
HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);/*TODO check if it is correct*/
HW_RST_Reset(resources.dwPrmBase, HW_RST2_TESLA);/*Just to ensure that the RST's are enabled*/
HW_RST_UnReset(resources.dwPrmBase, HW_RST2_TESLA);
printk("Calling the MMU_LOCK BaseValue");
*((REG_UWORD32 *)((u32)(resources.dwDmmuBase)+0x50)) = 0x400;
#else
......@@ -352,24 +350,16 @@ static DSP_STATUS WMD_BRD_Monitor(struct WMD_DEV_CONTEXT *hDevContext)
if ((temp & 0x03) != 0x03 || (temp & 0x03) != 0x02) {
/* IVA2 is not in ON state */
/* Read and set PM_PWSTCTRL_IVA2 to ON */
HW_PWR_PowerStateGet(resources.dwPrmBase, HW_PWR_DOMAIN_TESLA,
&pwrState);
HW_PWR_PowerStateSet(resources.dwPrmBase,
HW_PWR_DOMAIN_TESLA,
HW_PWR_STATE_ON);
HW_PWR_IVA2StateGet(resources.dwPrmBase, HW_PWR_DOMAIN_DSP,
&pwrState);
HW_PWR_IVA2PowerStateSet(resources.dwPrmBase,
HW_PWR_DOMAIN_DSP,
HW_PWR_STATE_ON);
/* Set the SW supervised state transition */
HW_PWR_CLKCTRL_IVA2RegSet(resources.dwCmBase, HW_SW_SUP_WAKEUP);
/* Wait until the state has moved to ON */
HW_PWR_IVA2StateGet(resources.dwPrmBase, HW_PWR_DOMAIN_DSP,
&pwrState);
&pwrState);
/* Disable Automatic transition */
HW_PWR_CLKCTRL_IVA2RegSet(resources.dwCmBase, HW_AUTOTRANS_DIS);
}
......@@ -616,6 +606,7 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
#endif
/* Let the DSP MMU run */
HW_MMU_Enable(resources.dwDmmuBase);
(void)CHNLSM_EnableInterrupt(pDevContext);
#ifdef OMAP_3430
......@@ -768,8 +759,6 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
* stale messages */
(void)CHNLSM_EnableInterrupt(pDevContext);
}
#else
(void)CHNLSM_EnableInterrupt(pDevContext);
#endif
if (DSP_SUCCEEDED(status)) {
#ifdef OMAP_3430
......@@ -780,13 +769,13 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
DBG_Trace(DBG_LEVEL7, "BRD_Start0: RM_RSTST_DSP = 0x%x \n",
temp);
#else
HW_RSTCTRL_RegGet(resources.dwPrmBase, &temp);
DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTCTRL_DSP = 0x%x \n",
temp);
HW_RSTST_RegGet(resources.dwPrmBase, &temp);
DBG_Trace(DBG_LEVEL7, "BRD_Start0: RM_RSTST_DSP = 0x%x \n",
temp);
/* Let DSP go */
HW_RSTCTRL_RegGet(resources.dwPrmBase, HW_RST1_TESLA, &temp);
DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTCTRL_DSP = 0x%x \n",
temp);
HW_RSTST_RegGet(resources.dwPrmBase, HW_RST1_TESLA, &temp);
DBG_Trace(DBG_LEVEL7, "BRD_Start0: RM_RSTST_DSP = 0x%x \n",
temp);
/* Let DSP go */
#endif
/* Let DSP go */
DBG_Trace(DBG_LEVEL7, "Unreset, WMD_BRD_Start\n");
......@@ -796,10 +785,10 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
/* release the RST1, DSP starts executing now .. */
#ifdef OMAP44XX
HW_RST_UnReset(resources.dwPrmBase, HW_RST1_TESLA);
HW_RSTST_RegGet(resources.dwPrmBase, &temp);
DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTST_DSP = 0x%x \n",
temp);
HW_RSTCTRL_RegGet(resources.dwPrmBase, &temp);
HW_RSTST_RegGet(resources.dwPrmBase, HW_RST1_TESLA, &temp);
DBG_Trace(DBG_LEVEL7, "BRD_Start: RM_RSTST_DSP = 0x%x \n",
temp);
HW_RSTCTRL_RegGet(resources.dwPrmBase, HW_RST1_TESLA, &temp);
#else
HW_RST_UnReset(resources.dwPrmBase, HW_RST1_IVA2);
HW_RSTST_RegGet(resources.dwPrmBase, HW_RST1_IVA2, &temp);
......@@ -890,12 +879,9 @@ static DSP_STATUS WMD_BRD_Stop(struct WMD_DEV_CONTEXT *hDevContext)
#ifdef OMAP44XX
DBG_Trace(DBG_LEVEL7, "Resetting DSP...");
printk("Stop:Disabling Clocks...");
HW_CLK_Disable (resources.dwCm1Base, HW_CLK_TESLA) ;
printk("Stop:Resetting DSP...");
HW_RST_Reset(resources.dwPrmBase, HW_RST1_TESLA);
/* Enable DSP */
printk("Stop:Enabling Clocks...");
HW_CLK_Enable (resources.dwCm1Base, HW_CLK_TESLA) ;
#else
HW_PWRST_IVA2RegGet(resources.dwPrmBase, &dspPwrState);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment