Commit c60ecec6 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Cacheops.h: Fix typo.
  [MIPS] Cobalt: Qube1 has no serial port so don't use it
  [MIPS] Cobalt: Fix ethernet interrupts for RaQ1
  [MIPS] Kconfig fixes for BCM47XX platform
parents c23f72ca 2e4f9582
...@@ -59,6 +59,8 @@ config BCM47XX ...@@ -59,6 +59,8 @@ config BCM47XX
select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN
select SSB select SSB
select SSB_DRIVER_MIPS select SSB_DRIVER_MIPS
select SSB_DRIVER_EXTIF
select SSB_PCICORE_HOSTMODE if PCI
select GENERIC_GPIO select GENERIC_GPIO
select SYS_HAS_EARLY_PRINTK select SYS_HAS_EARLY_PRINTK
select CFE select CFE
......
...@@ -4,10 +4,15 @@ ...@@ -4,10 +4,15 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/serial_reg.h> #include <linux/serial_reg.h>
#include <cobalt.h>
#define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000)) #define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000))
void prom_putchar(char c) void prom_putchar(char c)
{ {
if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
return;
while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE)) while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE))
; ;
......
...@@ -177,7 +177,7 @@ static char irq_tab_raq2[] __initdata = { ...@@ -177,7 +177,7 @@ static char irq_tab_raq2[] __initdata = {
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{ {
if (cobalt_board_id < COBALT_BRD_ID_QUBE2) if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
return irq_tab_qube1[slot]; return irq_tab_qube1[slot];
if (cobalt_board_id == COBALT_BRD_ID_RAQ2) if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
......
...@@ -64,7 +64,7 @@ ...@@ -64,7 +64,7 @@
#define Page_Invalidate_T 0x16 #define Page_Invalidate_T 0x16
/* /*
* R1000-specific cacheops * R10000-specific cacheops
* *
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops. * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
......
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