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linux
linux-davinci
Commits
c40b92e0
Commit
c40b92e0
authored
Apr 02, 2006
by
Ralf Baechle
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[MIPS] Ocelot 3: Fix build errors after the recent move of Marvell headers.
Signed-off-by:
Ralf Baechle
<
ralf@linux-mips.org
>
parent
088cf96a
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1
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arch/mips/momentum/ocelot_3/setup.c
arch/mips/momentum/ocelot_3/setup.c
+12
-12
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arch/mips/momentum/ocelot_3/setup.c
View file @
c40b92e0
...
...
@@ -329,22 +329,22 @@ void __init plat_setup(void)
/* shut down ethernet ports, just to be sure our memory doesn't get
* corrupted by random ethernet traffic.
*/
MV_WRITE
(
MV643
40
_ETH_TRANSMIT_QUEUE_COMMAND_REG
(
0
),
0xff
<<
8
);
MV_WRITE
(
MV643
40
_ETH_TRANSMIT_QUEUE_COMMAND_REG
(
1
),
0xff
<<
8
);
MV_WRITE
(
MV643
40
_ETH_RECEIVE_QUEUE_COMMAND_REG
(
0
),
0xff
<<
8
);
MV_WRITE
(
MV643
40
_ETH_RECEIVE_QUEUE_COMMAND_REG
(
1
),
0xff
<<
8
);
MV_WRITE
(
MV643
XX
_ETH_TRANSMIT_QUEUE_COMMAND_REG
(
0
),
0xff
<<
8
);
MV_WRITE
(
MV643
XX
_ETH_TRANSMIT_QUEUE_COMMAND_REG
(
1
),
0xff
<<
8
);
MV_WRITE
(
MV643
XX
_ETH_RECEIVE_QUEUE_COMMAND_REG
(
0
),
0xff
<<
8
);
MV_WRITE
(
MV643
XX
_ETH_RECEIVE_QUEUE_COMMAND_REG
(
1
),
0xff
<<
8
);
do
{}
while
(
MV_READ
(
MV643
40
_ETH_RECEIVE_QUEUE_COMMAND_REG
(
0
))
&
0xff
);
while
(
MV_READ
(
MV643
XX
_ETH_RECEIVE_QUEUE_COMMAND_REG
(
0
))
&
0xff
);
do
{}
while
(
MV_READ
(
MV643
40
_ETH_RECEIVE_QUEUE_COMMAND_REG
(
1
))
&
0xff
);
while
(
MV_READ
(
MV643
XX
_ETH_RECEIVE_QUEUE_COMMAND_REG
(
1
))
&
0xff
);
do
{}
while
(
MV_READ
(
MV643
40
_ETH_TRANSMIT_QUEUE_COMMAND_REG
(
0
))
&
0xff
);
while
(
MV_READ
(
MV643
XX
_ETH_TRANSMIT_QUEUE_COMMAND_REG
(
0
))
&
0xff
);
do
{}
while
(
MV_READ
(
MV643
40
_ETH_TRANSMIT_QUEUE_COMMAND_REG
(
1
))
&
0xff
);
MV_WRITE
(
MV643
40
_ETH_PORT_SERIAL_CONTROL_REG
(
0
),
MV_READ
(
MV643
40
_ETH_PORT_SERIAL_CONTROL_REG
(
0
))
&
~
1
);
MV_WRITE
(
MV643
40
_ETH_PORT_SERIAL_CONTROL_REG
(
1
),
MV_READ
(
MV643
40
_ETH_PORT_SERIAL_CONTROL_REG
(
1
))
&
~
1
);
while
(
MV_READ
(
MV643
XX
_ETH_TRANSMIT_QUEUE_COMMAND_REG
(
1
))
&
0xff
);
MV_WRITE
(
MV643
XX
_ETH_PORT_SERIAL_CONTROL_REG
(
0
),
MV_READ
(
MV643
XX
_ETH_PORT_SERIAL_CONTROL_REG
(
0
))
&
~
1
);
MV_WRITE
(
MV643
XX
_ETH_PORT_SERIAL_CONTROL_REG
(
1
),
MV_READ
(
MV643
XX
_ETH_PORT_SERIAL_CONTROL_REG
(
1
))
&
~
1
);
/* Turn off the Bit-Error LED */
OCELOT_FPGA_WRITE
(
0x80
,
CLR
);
...
...
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