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linux-davinci
Commit c0d5e170 authored by Kevin Hilman's avatar Kevin Hilman
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Revert "ARM: da830 - Add base DA830/OMAP-L137 SoC support" 

This reverts commit 40e1b943.
parent 23213a0e
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Showing with 9 additions and 2223 deletions
arch/arm/mach-davinci/Kconfig
View file @ c0d5e170
......@@ -6,9 +6,6 @@ config AINTC
config CP_INTC
bool
config ARCH_DAVINCI_DMx
bool
menu "TI DaVinci Implementations"
comment "DaVinci Core Type"
......@@ -16,21 +13,14 @@ comment "DaVinci Core Type"
config ARCH_DAVINCI_DM644x
bool "DaVinci 644x based system"
select AINTC
select ARCH_DAVINCI_DMx
config ARCH_DAVINCI_DM355
bool "DaVinci 355 based system"
select AINTC
select ARCH_DAVINCI_DMx
config ARCH_DAVINCI_DM646x
bool "DaVinci 646x based system"
select AINTC
select ARCH_DAVINCI_DMx
config ARCH_DAVINCI_DA830
bool "DA830/OMAP-L137 based system"
select CP_INTC
config ARCH_DAVINCI_DM365
bool "DaVinci 365 based system"
......
arch/arm/mach-davinci/Makefile
View file @ c0d5e170
......@@ -5,16 +5,15 @@
# Common objects
obj-y := time.o clock.o serial.o io.o psc.o \
gpio.o dma.o usb.o common.o sram.o
gpio.o devices.o dma.o usb.o common.o sram.o
obj-$(CONFIG_DAVINCI_MUX) += mux.o
# Chip specific
obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da830.o
obj-$(CONFIG_ARCH_DAVINCI_DM644x) += dm644x.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o
obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o
obj-$(CONFIG_AINTC) += irq.o
obj-$(CONFIG_CP_INTC) += cp_intc.o
......
arch/arm/mach-davinci/Makefile.boot
View file @ c0d5e170
ifeq ($(CONFIG_ARCH_DAVINCI_DA830),y)
ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y)
$(error Cannot enable DaVinci and DA830 platforms concurrently)
else
zreladdr-y := 0xc0008000
params_phys-y := 0xc0000100
initrd_phys-y := 0xc0800000
endif
else
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000
endif
arch/arm/mach-davinci/da830.c deleted 100644 → 0
View file @ 23213a0e
This diff is collapsed.
arch/arm/mach-davinci/devices-da830.c deleted 100644 → 0
View file @ 23213a0e
/*
* DA830/OMAP L137 platform device data
*
* Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
* Derived from code that was:
* Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
#include <mach/cputype.h>
#include <mach/common.h>
#include <mach/time.h>
#include <mach/da830.h>
#include "clock.h"
#define DA830_TPCC_BASE 0x01c00000
#define DA830_TPTC0_BASE 0x01c08000
#define DA830_TPTC1_BASE 0x01c08400
#define DA830_WDOG_BASE 0x01c21000 /* DA830_TIMER64P1_BASE */
#define DA830_I2C0_BASE 0x01c22000
#define DA830_EMAC_CPPI_PORT_BASE 0x01e20000
#define DA830_EMAC_CPGMACSS_BASE 0x01e22000
#define DA830_EMAC_CPGMAC_BASE 0x01e23000
#define DA830_EMAC_MDIO_BASE 0x01e24000
#define DA830_GPIO_BASE 0x01e26000
#define DA830_I2C1_BASE 0x01e28000
#define DA830_EMAC_CTRL_REG_OFFSET 0x3000
#define DA830_EMAC_MOD_REG_OFFSET 0x2000
#define DA830_EMAC_RAM_OFFSET 0x0000
#define DA830_MDIO_REG_OFFSET 0x4000
#define DA830_EMAC_CTRL_RAM_SIZE SZ_8K
static struct plat_serial8250_port da830_serial_pdata[] = {
{
.mapbase = DA830_UART0_BASE,
.irq = IRQ_DA830_UARTINT0,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 2,
},
{
.mapbase = DA830_UART1_BASE,
.irq = IRQ_DA830_UARTINT1,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 2,
},
{
.mapbase = DA830_UART2_BASE,
.irq = IRQ_DA830_UARTINT2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 2,
},
{
.flags = 0,
},
};
struct platform_device da830_serial_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = da830_serial_pdata,
},
};
static const s8 da830_dma_chan_no_event[] = {
20, 21,
-1
};
static struct edma_soc_info da830_edma_info = {
.n_channel = 32,
.n_region = 4,
.n_slot = 128,
.n_tc = 2,
.noevent = da830_dma_chan_no_event,
};
static struct resource da830_edma_resources[] = {
{
.name = "edma_cc",
.start = DA830_TPCC_BASE,
.end = DA830_TPCC_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "edma_tc0",
.start = DA830_TPTC0_BASE,
.end = DA830_TPTC0_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "edma_tc1",
.start = DA830_TPTC1_BASE,
.end = DA830_TPTC1_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DA830_TCERRINT0,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA830_CCERRINT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device da830_edma_device = {
.name = "edma",
.id = -1,
.dev = {
.platform_data = &da830_edma_info,
},
.num_resources = ARRAY_SIZE(da830_edma_resources),
.resource = da830_edma_resources,
};
int __init da830_register_edma(void)
{
return platform_device_register(&da830_edma_device);
}
static struct resource da830_i2c_resources0[] = {
{
.start = DA830_I2C0_BASE,
.end = DA830_I2C0_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DA830_I2CINT0,
.end = IRQ_DA830_I2CINT0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device da830_i2c_device0 = {
.name = "i2c_davinci",
.id = 1,
.num_resources = ARRAY_SIZE(da830_i2c_resources0),
.resource = da830_i2c_resources0,
};
static struct resource da830_i2c_resources1[] = {
{
.start = DA830_I2C1_BASE,
.end = DA830_I2C1_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DA830_I2CINT1,
.end = IRQ_DA830_I2CINT1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device da830_i2c_device1 = {
.name = "i2c_davinci",
.id = 2,
.num_resources = ARRAY_SIZE(da830_i2c_resources1),
.resource = da830_i2c_resources1,
};
int __init da830_register_i2c(int instance,
struct davinci_i2c_platform_data *pdata)
{
struct platform_device *pdev;
if (instance == 0)
pdev = &da830_i2c_device0;
else if (instance == 1)
pdev = &da830_i2c_device1;
else
return -EINVAL;
pdev->dev.platform_data = pdata;
return platform_device_register(pdev);
}
static struct resource da830_watchdog_resources[] = {
{
.start = DA830_WDOG_BASE,
.end = DA830_WDOG_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device davinci_wdt_device = {
.name = "watchdog",
.id = -1,
.num_resources = ARRAY_SIZE(da830_watchdog_resources),
.resource = da830_watchdog_resources,
};
int __init da830_register_watchdog(void)
{
return platform_device_register(&davinci_wdt_device);
}
static struct resource da830_emac_resources[] = {
{
.start = DA830_EMAC_CPPI_PORT_BASE,
.end = DA830_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_DA830_C0_RX_THRESH_PULSE,
.end = IRQ_DA830_C0_RX_THRESH_PULSE,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA830_C0_RX_PULSE,
.end = IRQ_DA830_C0_RX_PULSE,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA830_C0_TX_PULSE,
.end = IRQ_DA830_C0_TX_PULSE,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_DA830_C0_MISC_PULSE,
.end = IRQ_DA830_C0_MISC_PULSE,
.flags = IORESOURCE_IRQ,
},
};
struct emac_platform_data da830_emac_pdata = {
.ctrl_reg_offset = DA830_EMAC_CTRL_REG_OFFSET,
.ctrl_mod_reg_offset = DA830_EMAC_MOD_REG_OFFSET,
.ctrl_ram_offset = DA830_EMAC_RAM_OFFSET,
.mdio_reg_offset = DA830_MDIO_REG_OFFSET,
.ctrl_ram_size = DA830_EMAC_CTRL_RAM_SIZE,
.version = EMAC_VERSION_2,
};
static struct platform_device da830_emac_device = {
.name = "davinci_emac",
.id = 1,
.dev = {
.platform_data = &da830_emac_pdata,
},
.num_resources = ARRAY_SIZE(da830_emac_resources),
.resource = da830_emac_resources,
};
int __init da830_register_emac(void)
{
return platform_device_register(&da830_emac_device);
}
arch/arm/mach-davinci/include/mach/cputype.h
View file @ c0d5e170
......@@ -31,7 +31,6 @@ struct davinci_id {
#define DAVINCI_CPU_ID_DM6467 0x64670000
#define DAVINCI_CPU_ID_DM355 0x03550000
#define DAVINCI_CPU_ID_DM365 0x03650000
#define DAVINCI_CPU_ID_DA830 0x08300000
#define IS_DAVINCI_CPU(type, id) \
static inline int is_davinci_ ##type(void) \
......@@ -43,7 +42,6 @@ IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
#ifdef CONFIG_ARCH_DAVINCI_DM644x
#define cpu_is_davinci_dm644x() is_davinci_dm644x()
......@@ -69,10 +67,4 @@ IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
#define cpu_is_davinci_dm365() 0
#endif
#ifdef CONFIG_ARCH_DAVINCI_DA830
#define cpu_is_davinci_da830() is_davinci_da830()
#else
#define cpu_is_davinci_da830() 0
#endif
#endif
arch/arm/mach-davinci/include/mach/da830.h deleted 100644 → 0
View file @ 23213a0e
/*
* Chip specific defines for DA830/OMAP L137 SoC
*
* Author: Mark A. Greer <mgreer@mvista.com>
*
* 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARCH_DAVINCI_DA830_H
#define __ASM_ARCH_DAVINCI_DA830_H
#include <mach/serial.h>
#include <mach/edma.h>
#include <mach/i2c.h>
#include <mach/emac.h>
/*
* The cp_intc interrupt controller for the da830 isn't in the same
* chunk of physical memory space as the other registers (like it is
* on the davincis) so it needs to be mapped separately. It will be
* mapped early on when the I/O space is mapped and we'll put it just
* before the I/O space in the processor's virtual memory space.
*/
#define DA830_CP_INTC_BASE 0xfffee000
#define DA830_CP_INTC_SIZE SZ_8K
#define DA830_CP_INTC_VIRT (IO_VIRT - DA830_CP_INTC_SIZE - SZ_4K)
#define DA830_BOOT_CFG_BASE (IO_PHYS + 0x14000)
void __init da830_init(void);
int da830_register_edma(void);
int da830_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
int da830_register_watchdog(void);
int da830_register_emac(void);
extern struct platform_device da830_serial_device;
extern struct emac_platform_data da830_emac_pdata;
extern const short da830_emif25_pins[];
extern const short da830_spi0_pins[];
extern const short da830_spi1_pins[];
extern const short da830_mmc_sd_pins[];
extern const short da830_uart0_pins[];
extern const short da830_uart1_pins[];
extern const short da830_uart2_pins[];
extern const short da830_usb20_pins[];
extern const short da830_usb11_pins[];
extern const short da830_uhpi_pins[];
extern const short da830_cpgmac_pins[];
extern const short da830_emif3c_pins[];
extern const short da830_mcasp0_pins[];
extern const short da830_mcasp1_pins[];
extern const short da830_mcasp2_pins[];
extern const short da830_i2c0_pins[];
extern const short da830_i2c1_pins[];
extern const short da830_lcdcntl_pins[];
extern const short da830_pwm_pins[];
extern const short da830_ecap0_pins[];
extern const short da830_ecap1_pins[];
extern const short da830_ecap2_pins[];
extern const short da830_eqep0_pins[];
extern const short da830_eqep1_pins[];
int da830_pinmux_setup(const short pins[]);
#endif /* __ASM_ARCH_DAVINCI_DA830_H */
arch/arm/mach-davinci/include/mach/edma.h
View file @ c0d5e170
......@@ -139,54 +139,6 @@ struct edmacc_param {
#define DAVINCI_DMA_PWM1 53
#define DAVINCI_DMA_PWM2 54
/* DA830 specific EDMA3 information */
#define EDMA_DA830_NUM_DMACH 32
#define EDMA_DA830_NUM_TCC 32
#define EDMA_DA830_NUM_PARAMENTRY 128
#define EDMA_DA830_NUM_EVQUE 2
#define EDMA_DA830_NUM_TC 2
#define EDMA_DA830_CHMAP_EXIST 0
#define EDMA_DA830_NUM_REGIONS 4
#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu
#define DA830_DMACH2EVENT_MAP1 0x00000000u
#define DA830_EDMA_ARM_OWN 0x30FFCCFFu
/* DA830 specific EDMA3 Events Information */
enum DA830_edma_ch {
DA830_DMACH_MCASP0_RX,
DA830_DMACH_MCASP0_TX,
DA830_DMACH_MCASP1_RX,
DA830_DMACH_MCASP1_TX,
DA830_DMACH_MCASP2_RX,
DA830_DMACH_MCASP2_TX,
DA830_DMACH_GPIO_BNK0INT,
DA830_DMACH_GPIO_BNK1INT,
DA830_DMACH_UART0_RX,
DA830_DMACH_UART0_TX,
DA830_DMACH_TMR64P0_EVTOUT12,
DA830_DMACH_TMR64P0_EVTOUT34,
DA830_DMACH_UART1_RX,
DA830_DMACH_UART1_TX,
DA830_DMACH_SPI0_RX,
DA830_DMACH_SPI0_TX,
DA830_DMACH_MMCSD_RX,
DA830_DMACH_MMCSD_TX,
DA830_DMACH_SPI1_RX,
DA830_DMACH_SPI1_TX,
DA830_DMACH_DMAX_EVTOUT6,
DA830_DMACH_DMAX_EVTOUT7,
DA830_DMACH_GPIO_BNK2INT,
DA830_DMACH_GPIO_BNK3INT,
DA830_DMACH_I2C0_RX,
DA830_DMACH_I2C0_TX,
DA830_DMACH_I2C1_RX,
DA830_DMACH_I2C1_TX,
DA830_DMACH_GPIO_BNK4INT,
DA830_DMACH_GPIO_BNK5INT,
DA830_DMACH_UART2_RX,
DA830_DMACH_UART2_TX
};
/*ch_status paramater of callback function possible values*/
#define DMA_COMPLETE 1
#define DMA_CC_ERROR 2
......
arch/arm/mach-davinci/include/mach/irqs.h
View file @ c0d5e170
......@@ -99,6 +99,9 @@
#define IRQ_EMUINT 63
#define DAVINCI_N_AINTC_IRQ 64
#define DAVINCI_N_GPIO 104
#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
......@@ -239,108 +242,4 @@
#define IRQ_DM365_TCERRINT3 62
#define IRQ_DM365_EMUINT 63
/* DA830 interrupts */
#define IRQ_DA830_COMMTX 0
#define IRQ_DA830_COMMRX 1
#define IRQ_DA830_NINT 2
#define IRQ_DA830_EVTOUT0 3
#define IRQ_DA830_EVTOUT1 4
#define IRQ_DA830_EVTOUT2 5
#define IRQ_DA830_EVTOUT3 6
#define IRQ_DA830_EVTOUT4 7
#define IRQ_DA830_EVTOUT5 8
#define IRQ_DA830_EVTOUT6 9
#define IRQ_DA830_EVTOUT7 10
#define IRQ_DA830_CCINT0 11
#define IRQ_DA830_CCERRINT 12
#define IRQ_DA830_TCERRINT0 13
#define IRQ_DA830_AEMIFINT 14
#define IRQ_DA830_I2CINT0 15
#define IRQ_DA830_MMCSDINT0 16
#define IRQ_DA830_MMCSDINT1 17
#define IRQ_DA830_ALLINT0 18
#define IRQ_DA830_RTC 19
#define IRQ_DA830_SPINT0 20
#define IRQ_DA830_TINT12_0 21
#define IRQ_DA830_TINT34_0 22
#define IRQ_DA830_TINT12_1 23
#define IRQ_DA830_TINT34_1 24
#define IRQ_DA830_UARTINT0 25
#define IRQ_DA830_KEYMGRINT 26
#define IRQ_DA830_SECINT 26
#define IRQ_DA830_SECKEYERR 26
#define IRQ_DA830_MPUERR 27
#define IRQ_DA830_IOPUERR 27
#define IRQ_DA830_BOOTCFGERR 27
#define IRQ_DA830_CHIPINT0 28
#define IRQ_DA830_CHIPINT1 29
#define IRQ_DA830_CHIPINT2 30
#define IRQ_DA830_CHIPINT3 31
#define IRQ_DA830_TCERRINT1 32
#define IRQ_DA830_C0_RX_THRESH_PULSE 33
#define IRQ_DA830_C0_RX_PULSE 34
#define IRQ_DA830_C0_TX_PULSE 35
#define IRQ_DA830_C0_MISC_PULSE 36
#define IRQ_DA830_C1_RX_THRESH_PULSE 37
#define IRQ_DA830_C1_RX_PULSE 38
#define IRQ_DA830_C1_TX_PULSE 39
#define IRQ_DA830_C1_MISC_PULSE 40
#define IRQ_DA830_MEMERR 41
#define IRQ_DA830_GPIO0 42
#define IRQ_DA830_GPIO1 43
#define IRQ_DA830_GPIO2 44
#define IRQ_DA830_GPIO3 45
#define IRQ_DA830_GPIO4 46
#define IRQ_DA830_GPIO5 47
#define IRQ_DA830_GPIO6 48
#define IRQ_DA830_GPIO7 49
#define IRQ_DA830_GPIO8 50
#define IRQ_DA830_I2CINT1 51
#define IRQ_DA830_LCDINT 52
#define IRQ_DA830_UARTINT1 53
#define IRQ_DA830_MCASPINT 54
#define IRQ_DA830_ALLINT1 55
#define IRQ_DA830_SPINT1 56
#define IRQ_DA830_UHPI_INT1 57
#define IRQ_DA830_USB_INT 58
#define IRQ_DA830_IRQN 59
#define IRQ_DA830_RWAKEUP 60
#define IRQ_DA830_UARTINT2 61
#define IRQ_DA830_DFTSSINT 62
#define IRQ_DA830_EHRPWM0 63
#define IRQ_DA830_EHRPWM0TZ 64
#define IRQ_DA830_EHRPWM1 65
#define IRQ_DA830_EHRPWM1TZ 66
#define IRQ_DA830_EHRPWM2 67
#define IRQ_DA830_EHRPWM2TZ 68
#define IRQ_DA830_ECAP0 69
#define IRQ_DA830_ECAP1 70
#define IRQ_DA830_ECAP2 71
#define IRQ_DA830_EQEP0 72
#define IRQ_DA830_EQEP1 73
#define IRQ_DA830_T12CMPINT0_0 74
#define IRQ_DA830_T12CMPINT1_0 75
#define IRQ_DA830_T12CMPINT2_0 76
#define IRQ_DA830_T12CMPINT3_0 77
#define IRQ_DA830_T12CMPINT4_0 78
#define IRQ_DA830_T12CMPINT5_0 79
#define IRQ_DA830_T12CMPINT6_0 80
#define IRQ_DA830_T12CMPINT7_0 81
#define IRQ_DA830_T12CMPINT0_1 82
#define IRQ_DA830_T12CMPINT1_1 83
#define IRQ_DA830_T12CMPINT2_1 84
#define IRQ_DA830_T12CMPINT3_1 85
#define IRQ_DA830_T12CMPINT4_1 86
#define IRQ_DA830_T12CMPINT5_1 87
#define IRQ_DA830_T12CMPINT6_1 88
#define IRQ_DA830_T12CMPINT7_1 89
#define IRQ_DA830_ARMCLKSTOPREQ 90
#define DA830_N_CP_INTC_IRQ 96
/* da830 currently has the most gpio pins (128) */
#define DAVINCI_N_GPIO 128
/* da830 currently has the most irqs so use DA830_N_CP_INTC_IRQ */
#define NR_IRQS (DA830_N_CP_INTC_IRQ + DAVINCI_N_GPIO)
#endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach-davinci/include/mach/memory.h
View file @ c0d5e170
......@@ -20,16 +20,9 @@
/**************************************************************************
* Definitions
**************************************************************************/
#define DAVINCI_DDR_BASE 0x80000000
#define DA830_DDR_BASE 0xc0000000
#define DAVINCI_DDR_BASE 0x80000000
#if defined(CONFIG_ARCH_DAVINCI_DA830) && defined(CONFIG_ARCH_DAVINCI_DMx)
#error Cannot enable DaVinci and DA830 platforms concurrently
#elif defined(CONFIG_ARCH_DAVINCI_DA830)
#define PHYS_OFFSET DA830_DDR_BASE
#else
#define PHYS_OFFSET DAVINCI_DDR_BASE
#endif
/*
* Increase size of DMA-consistent memory region
......
arch/arm/mach-davinci/include/mach/mux.h
View file @ c0d5e170
......@@ -242,410 +242,6 @@ enum davinci_dm365_index {
DM365_EVT26_MMC0_RX,
};
enum da830_index {
DA830_GPIO7_14,
DA830_RTCK,
DA830_GPIO7_15,
DA830_EMU_0,
DA830_EMB_SDCKE,
DA830_EMB_CLK_GLUE,
DA830_EMB_CLK,
DA830_NEMB_CS_0,
DA830_NEMB_CAS,
DA830_NEMB_RAS,
DA830_NEMB_WE,
DA830_EMB_BA_1,
DA830_EMB_BA_0,
DA830_EMB_A_0,
DA830_EMB_A_1,
DA830_EMB_A_2,
DA830_EMB_A_3,
DA830_EMB_A_4,
DA830_EMB_A_5,
DA830_GPIO7_0,
DA830_GPIO7_1,
DA830_GPIO7_2,
DA830_GPIO7_3,
DA830_GPIO7_4,
DA830_GPIO7_5,
DA830_GPIO7_6,
DA830_GPIO7_7,
DA830_EMB_A_6,
DA830_EMB_A_7,
DA830_EMB_A_8,
DA830_EMB_A_9,
DA830_EMB_A_10,
DA830_EMB_A_11,
DA830_EMB_A_12,
DA830_EMB_D_31,
DA830_GPIO7_8,
DA830_GPIO7_9,
DA830_GPIO7_10,
DA830_GPIO7_11,
DA830_GPIO7_12,
DA830_GPIO7_13,
DA830_GPIO3_13,
DA830_EMB_D_30,
DA830_EMB_D_29,
DA830_EMB_D_28,
DA830_EMB_D_27,
DA830_EMB_D_26,
DA830_EMB_D_25,
DA830_EMB_D_24,
DA830_EMB_D_23,
DA830_EMB_D_22,
DA830_EMB_D_21,
DA830_EMB_D_20,
DA830_EMB_D_19,
DA830_EMB_D_18,
DA830_EMB_D_17,
DA830_EMB_D_16,
DA830_NEMB_WE_DQM_3,
DA830_NEMB_WE_DQM_2,
DA830_EMB_D_0,
DA830_EMB_D_1,
DA830_EMB_D_2,
DA830_EMB_D_3,
DA830_EMB_D_4,
DA830_EMB_D_5,
DA830_EMB_D_6,
DA830_GPIO6_0,
DA830_GPIO6_1,
DA830_GPIO6_2,
DA830_GPIO6_3,
DA830_GPIO6_4,
DA830_GPIO6_5,
DA830_GPIO6_6,
DA830_EMB_D_7,
DA830_EMB_D_8,
DA830_EMB_D_9,
DA830_EMB_D_10,
DA830_EMB_D_11,
DA830_EMB_D_12,
DA830_EMB_D_13,
DA830_EMB_D_14,
DA830_GPIO6_7,
DA830_GPIO6_8,
DA830_GPIO6_9,
DA830_GPIO6_10,
DA830_GPIO6_11,
DA830_GPIO6_12,
DA830_GPIO6_13,
DA830_GPIO6_14,
DA830_EMB_D_15,
DA830_NEMB_WE_DQM_1,
DA830_NEMB_WE_DQM_0,
DA830_SPI0_SOMI_0,
DA830_SPI0_SIMO_0,
DA830_SPI0_CLK,
DA830_NSPI0_ENA,
DA830_NSPI0_SCS_0,
DA830_EQEP0I,
DA830_EQEP0S,
DA830_EQEP1I,
DA830_NUART0_CTS,
DA830_NUART0_RTS,
DA830_EQEP0A,
DA830_EQEP0B,
DA830_GPIO6_15,
DA830_GPIO5_14,
DA830_GPIO5_15,
DA830_GPIO5_0,
DA830_GPIO5_1,
DA830_GPIO5_2,
DA830_GPIO5_3,
DA830_GPIO5_4,
DA830_SPI1_SOMI_0,
DA830_SPI1_SIMO_0,
DA830_SPI1_CLK,
DA830_UART0_RXD,
DA830_UART0_TXD,
DA830_AXR1_10,
DA830_AXR1_11,
DA830_NSPI1_ENA,
DA830_I2C1_SCL,
DA830_I2C1_SDA,
DA830_EQEP1S,
DA830_I2C0_SDA,
DA830_I2C0_SCL,
DA830_UART2_RXD,
DA830_TM64P0_IN12,
DA830_TM64P0_OUT12,
DA830_GPIO5_5,
DA830_GPIO5_6,
DA830_GPIO5_7,
DA830_GPIO5_8,
DA830_GPIO5_9,
DA830_GPIO5_10,
DA830_GPIO5_11,
DA830_GPIO5_12,
DA830_NSPI1_SCS_0,
DA830_USB0_DRVVBUS,
DA830_AHCLKX0,
DA830_ACLKX0,
DA830_AFSX0,
DA830_AHCLKR0,
DA830_ACLKR0,
DA830_AFSR0,
DA830_UART2_TXD,
DA830_AHCLKX2,
DA830_ECAP0_APWM0,
DA830_RMII_MHZ_50_CLK,
DA830_ECAP1_APWM1,
DA830_USB_REFCLKIN,
DA830_GPIO5_13,
DA830_GPIO4_15,
DA830_GPIO2_11,
DA830_GPIO2_12,
DA830_GPIO2_13,
DA830_GPIO2_14,
DA830_GPIO2_15,
DA830_GPIO3_12,
DA830_AMUTE0,
DA830_AXR0_0,
DA830_AXR0_1,
DA830_AXR0_2,
DA830_AXR0_3,
DA830_AXR0_4,
DA830_AXR0_5,
DA830_AXR0_6,
DA830_RMII_TXD_0,
DA830_RMII_TXD_1,
DA830_RMII_TXEN,
DA830_RMII_CRS_DV,
DA830_RMII_RXD_0,
DA830_RMII_RXD_1,
DA830_RMII_RXER,
DA830_AFSR2,
DA830_ACLKX2,
DA830_AXR2_3,
DA830_AXR2_2,
DA830_AXR2_1,
DA830_AFSX2,
DA830_ACLKR2,
DA830_NRESETOUT,
DA830_GPIO3_0,
DA830_GPIO3_1,
DA830_GPIO3_2,
DA830_GPIO3_3,
DA830_GPIO3_4,
DA830_GPIO3_5,
DA830_GPIO3_6,
DA830_AXR0_7,
DA830_AXR0_8,
DA830_UART1_RXD,
DA830_UART1_TXD,
DA830_AXR0_11,
DA830_AHCLKX1,
DA830_ACLKX1,
DA830_AFSX1,
DA830_MDIO_CLK,
DA830_MDIO_D,
DA830_AXR0_9,
DA830_AXR0_10,
DA830_EPWM0B,
DA830_EPWM0A,
DA830_EPWMSYNCI,
DA830_AXR2_0,
DA830_EPWMSYNC0,
DA830_GPIO3_7,
DA830_GPIO3_8,
DA830_GPIO3_9,
DA830_GPIO3_10,
DA830_GPIO3_11,
DA830_GPIO3_14,
DA830_GPIO3_15,
DA830_GPIO4_10,
DA830_AHCLKR1,
DA830_ACLKR1,
DA830_AFSR1,
DA830_AMUTE1,
DA830_AXR1_0,
DA830_AXR1_1,
DA830_AXR1_2,
DA830_AXR1_3,
DA830_ECAP2_APWM2,
DA830_EHRPWMGLUETZ,
DA830_EQEP1A,
DA830_GPIO4_11,
DA830_GPIO4_12,
DA830_GPIO4_13,
DA830_GPIO4_14,
DA830_GPIO4_0,
DA830_GPIO4_1,
DA830_GPIO4_2,
DA830_GPIO4_3,
DA830_AXR1_4,
DA830_AXR1_5,
DA830_AXR1_6,
DA830_AXR1_7,
DA830_AXR1_8,
DA830_AXR1_9,
DA830_EMA_D_0,
DA830_EMA_D_1,
DA830_EQEP1B,
DA830_EPWM2B,
DA830_EPWM2A,
DA830_EPWM1B,
DA830_EPWM1A,
DA830_MMCSD_DAT_0,
DA830_MMCSD_DAT_1,
DA830_UHPI_HD_0,
DA830_UHPI_HD_1,
DA830_GPIO4_4,
DA830_GPIO4_5,
DA830_GPIO4_6,
DA830_GPIO4_7,
DA830_GPIO4_8,
DA830_GPIO4_9,
DA830_GPIO0_0,
DA830_GPIO0_1,
DA830_EMA_D_2,
DA830_EMA_D_3,
DA830_EMA_D_4,
DA830_EMA_D_5,
DA830_EMA_D_6,
DA830_EMA_D_7,
DA830_EMA_D_8,
DA830_EMA_D_9,
DA830_MMCSD_DAT_2,
DA830_MMCSD_DAT_3,
DA830_MMCSD_DAT_4,
DA830_MMCSD_DAT_5,
DA830_MMCSD_DAT_6,
DA830_MMCSD_DAT_7,
DA830_UHPI_HD_8,
DA830_UHPI_HD_9,
DA830_UHPI_HD_2,
DA830_UHPI_HD_3,
DA830_UHPI_HD_4,
DA830_UHPI_HD_5,
DA830_UHPI_HD_6,
DA830_UHPI_HD_7,
DA830_LCD_D_8,
DA830_LCD_D_9,
DA830_GPIO0_2,
DA830_GPIO0_3,
DA830_GPIO0_4,
DA830_GPIO0_5,
DA830_GPIO0_6,
DA830_GPIO0_7,
DA830_GPIO0_8,
DA830_GPIO0_9,
DA830_EMA_D_10,
DA830_EMA_D_11,
DA830_EMA_D_12,
DA830_EMA_D_13,
DA830_EMA_D_14,
DA830_EMA_D_15,
DA830_EMA_A_0,
DA830_EMA_A_1,
DA830_UHPI_HD_10,
DA830_UHPI_HD_11,
DA830_UHPI_HD_12,
DA830_UHPI_HD_13,
DA830_UHPI_HD_14,
DA830_UHPI_HD_15,
DA830_LCD_D_7,
DA830_MMCSD_CLK,
DA830_LCD_D_10,
DA830_LCD_D_11,
DA830_LCD_D_12,
DA830_LCD_D_13,
DA830_LCD_D_14,
DA830_LCD_D_15,
DA830_UHPI_HCNTL0,
DA830_GPIO0_10,
DA830_GPIO0_11,
DA830_GPIO0_12,
DA830_GPIO0_13,
DA830_GPIO0_14,
DA830_GPIO0_15,
DA830_GPIO1_0,
DA830_GPIO1_1,
DA830_EMA_A_2,
DA830_EMA_A_3,
DA830_EMA_A_4,
DA830_EMA_A_5,
DA830_EMA_A_6,
DA830_EMA_A_7,
DA830_EMA_A_8,
DA830_EMA_A_9,
DA830_MMCSD_CMD,
DA830_LCD_D_6,
DA830_LCD_D_3,
DA830_LCD_D_2,
DA830_LCD_D_1,
DA830_LCD_D_0,
DA830_LCD_PCLK,
DA830_LCD_HSYNC,
DA830_UHPI_HCNTL1,
DA830_GPIO1_2,
DA830_GPIO1_3,
DA830_GPIO1_4,
DA830_GPIO1_5,
DA830_GPIO1_6,
DA830_GPIO1_7,
DA830_GPIO1_8,
DA830_GPIO1_9,
DA830_EMA_A_10,
DA830_EMA_A_11,
DA830_EMA_A_12,
DA830_EMA_BA_1,
DA830_EMA_BA_0,
DA830_EMA_CLK,
DA830_EMA_SDCKE,
DA830_NEMA_CAS,
DA830_LCD_VSYNC,
DA830_NLCD_AC_ENB_CS,
DA830_LCD_MCLK,
DA830_LCD_D_5,
DA830_LCD_D_4,
DA830_OBSCLK,
DA830_NEMA_CS_4,
DA830_UHPI_HHWIL,
DA830_AHCLKR2,
DA830_GPIO1_10,
DA830_GPIO1_11,
DA830_GPIO1_12,
DA830_GPIO1_13,
DA830_GPIO1_14,
DA830_GPIO1_15,
DA830_GPIO2_0,
DA830_GPIO2_1,
DA830_NEMA_RAS,
DA830_NEMA_WE,
DA830_NEMA_CS_0,
DA830_NEMA_CS_2,
DA830_NEMA_CS_3,
DA830_NEMA_OE,
DA830_NEMA_WE_DQM_1,
DA830_NEMA_WE_DQM_0,
DA830_NEMA_CS_5,
DA830_UHPI_HRNW,
DA830_NUHPI_HAS,
DA830_NUHPI_HCS,
DA830_NUHPI_HDS1,
DA830_NUHPI_HDS2,
DA830_NUHPI_HINT,
DA830_AXR0_12,
DA830_AMUTE2,
DA830_AXR0_13,
DA830_AXR0_14,
DA830_AXR0_15,
DA830_GPIO2_2,
DA830_GPIO2_3,
DA830_GPIO2_4,
DA830_GPIO2_5,
DA830_GPIO2_6,
DA830_GPIO2_7,
DA830_GPIO2_8,
DA830_GPIO2_9,
DA830_EMA_WAIT_0,
DA830_NUHPI_HRDY,
DA830_GPIO2_10,
};
#ifdef CONFIG_DAVINCI_MUX
/* setup pin muxing */
extern int davinci_cfg_reg(unsigned long reg_cfg);
......
arch/arm/mach-davinci/include/mach/psc.h
View file @ c0d5e170
......@@ -136,45 +136,6 @@
#define DM646X_LPSC_TIMER1 35
#define DM646X_LPSC_ARM_INTC 45
#define DA830_LPSC0_TPCC 0
#define DA830_LPSC0_TPTC0 1
#define DA830_LPSC0_TPTC1 2
#define DA830_LPSC0_EMIF25 3
#define DA830_LPSC0_SPI0 4
#define DA830_LPSC0_MMC_SD 5
#define DA830_LPSC0_AINTC 6
#define DA830_LPSC0_ARM_RAM_ROM 7
#define DA830_LPSC0_SECU_MGR 8
#define DA830_LPSC0_UART0 9
#define DA830_LPSC0_SCR0_SS 10
#define DA830_LPSC0_SCR1_SS 11
#define DA830_LPSC0_SCR2_SS 12
#define DA830_LPSC0_DMAX 13
#define DA830_LPSC0_ARM 14
#define DA830_LPSC0_GEM 15
#define DA830_LPSC1_USB20 1
#define DA830_LPSC1_USB11 2
#define DA830_LPSC1_GPIO 3
#define DA830_LPSC1_UHPI 4
#define DA830_LPSC1_CPGMAC 5
#define DA830_LPSC1_EMIF3C 6
#define DA830_LPSC1_McASP0 7
#define DA830_LPSC1_McASP1 8
#define DA830_LPSC1_McASP2 9
#define DA830_LPSC1_SPI1 10
#define DA830_LPSC1_I2C 11
#define DA830_LPSC1_UART1 12
#define DA830_LPSC1_UART2 13
#define DA830_LPSC1_LCDC 16
#define DA830_LPSC1_PWM 17
#define DA830_LPSC1_ECAP 20
#define DA830_LPSC1_EQEP 21
#define DA830_LPSC1_SCR_P0_SS 24
#define DA830_LPSC1_SCR_P1_SS 25
#define DA830_LPSC1_CR_P3_SS 26
#define DA830_LPSC1_L3_CBA_RAM 31
extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
unsigned int id, char enable);
......
arch/arm/mach-davinci/include/mach/serial.h
View file @ c0d5e170
......@@ -18,10 +18,6 @@
#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
#define DA830_UART0_BASE (IO_PHYS + 0x042000)
#define DA830_UART1_BASE (IO_PHYS + 0x10c000)
#define DA830_UART2_BASE (IO_PHYS + 0x10d000)
/* DaVinci UART register offsets */
#define UART_DAVINCI_PWREMU 0x0c
#define UART_DM646X_SCR 0x10
......
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