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linux
linux-davinci
Commits
b65a75b8
Commit
b65a75b8
authored
Oct 11, 2008
by
Ralf Baechle
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MIPS: IP checksums: Optimize adjust of sum on buffers of odd alignment.
Signed-off-by:
Ralf Baechle
<
ralf@linux-mips.org
>
parent
60724ca5
Changes
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24 additions
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11 deletions
+24
-11
arch/mips/lib/csum_partial.S
arch/mips/lib/csum_partial.S
+24
-11
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arch/mips/lib/csum_partial.S
View file @
b65a75b8
...
...
@@ -270,13 +270,20 @@ LEAF(csum_partial)
#endif
/
*
odd
buffer
alignment
?
*/
beqz
t7
,
1
f
nop
sll
v1
,
sum
,
8
#ifdef CPU_MIPSR2
wsbh
v1
,
sum
movn
sum
,
v1
,
t7
#else
beqz
t7
,
1
f
/*
odd
buffer
alignment
?
*/
lui
v1
,
0x00ff
addu
v1
,
0x00ff
and
t0
,
sum
,
v1
sll
t0
,
t0
,
8
srl
sum
,
sum
,
8
or
sum
,
v1
andi
sum
,
0xffff
and
sum
,
sum
,
v1
or
sum
,
sum
,
t0
1
:
#endif
.
set
reorder
/
*
Add
the
passed
partial
csum
.
*/
ADDC32
(
sum
,
a2
)
...
...
@@ -663,14 +670,20 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc)
addu
sum
,
v1
#endif
/
*
odd
buffer
alignment
?
*/
beqz
odd
,
1
f
nop
sll
v1
,
sum
,
8
#ifdef CPU_MIPSR2
wsbh
v1
,
sum
movn
sum
,
v1
,
odd
#else
beqz
odd
,
1
f
/*
odd
buffer
alignment
?
*/
lui
v1
,
0x00ff
addu
v1
,
0x00ff
and
t0
,
sum
,
v1
sll
t0
,
t0
,
8
srl
sum
,
sum
,
8
or
sum
,
v1
andi
sum
,
0xffff
and
sum
,
sum
,
v1
or
sum
,
sum
,
t0
1
:
#endif
.
set
reorder
ADDC32
(
sum
,
psum
)
jr
ra
...
...
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