Commit ae6bf7f1 authored by Mark A. Greer's avatar Mark A. Greer Committed by Kevin Hilman

ARM: Add writethrough dcache support for ARM926EJS processor

The ARM kernel supports writethrough data cache via the
CONFIG_CPU_DCACHE_WRITETHROUGH option.  However, that
functionality wasn't implemented in the arch/arm/boot/compressed
code.  It is now necessary due to a new ARM926EJS processor
that has an issue with writeback data cache.
Signed-off-by: default avatarMark A. Greer <mgreer@mvista.com>
parent e40152ee
...@@ -420,7 +420,11 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size ...@@ -420,7 +420,11 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
orr r1, r1, #3 << 10 orr r1, r1, #3 << 10
add r2, r3, #16384 add r2, r3, #16384
1: cmp r1, r9 @ if virt > start of RAM 1: cmp r1, r9 @ if virt > start of RAM
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
orrhs r1, r1, #0x08 @ set cacheable
#else
orrhs r1, r1, #0x0c @ set cacheable, bufferable orrhs r1, r1, #0x0c @ set cacheable, bufferable
#endif
cmp r1, r10 @ if virt > end of RAM cmp r1, r10 @ if virt > end of RAM
bichs r1, r1, #0x0c @ clear cacheable, bufferable bichs r1, r1, #0x0c @ clear cacheable, bufferable
str r1, [r0], #4 @ 1:1 mapping str r1, [r0], #4 @ 1:1 mapping
...@@ -444,6 +448,11 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size ...@@ -444,6 +448,11 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
mov pc, lr mov pc, lr
ENDPROC(__setup_mmu) ENDPROC(__setup_mmu)
__arm926ejs_mmu_cache_on:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
mov r0, #4 @ put dcache in WT mode
mcr p15, 7, r0, c15, c0, 0
#endif
__armv4_mmu_cache_on: __armv4_mmu_cache_on:
mov r12, lr mov r12, lr
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
...@@ -662,6 +671,12 @@ proc_types: ...@@ -662,6 +671,12 @@ proc_types:
W(b) __armv4_mpu_cache_off W(b) __armv4_mpu_cache_off
W(b) __armv4_mpu_cache_flush W(b) __armv4_mpu_cache_flush
.word 0x41069260 @ ARM926EJ-S (v5TEJ)
.word 0xff0ffff0
b __arm926ejs_mmu_cache_on
b __armv4_mmu_cache_off
b __armv5tej_mmu_cache_flush
.word 0x00007000 @ ARM7 IDs .word 0x00007000 @ ARM7 IDs
.word 0x0000f000 .word 0x0000f000
mov pc, lr mov pc, lr
......
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