Commit adb5ea75 authored by Paul Walmsley's avatar Paul Walmsley Committed by Tony Lindgren

omap2 clock: add support for inverted enable bits

On 3430ES2 (and presumably beyond), some clock tree branches from
DPLL3 & 4 can be powered down by setting 'PWRDN' bits in CM_CLKEN_PLL.
It appears that an easy way to power these branches down in our
existing clock framework is to use the PWRDN bits as clock enable bits
for the specific DPLL branches they affect.  The problem with this is
that the meaning of a set PWRDN bit is 'disable,' not 'enable.'  So,
introduce a new clock flag, INVERT_ENABLE, that clears the bit on
'clock enable,' and sets the bit on 'clock disable.'  This flag is used
on all PWRDN clock branches in the 3430 clock framework.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 926865d2
...@@ -170,6 +170,11 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name) ...@@ -170,6 +170,11 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name)
}; };
/*
* Note: We don't need special code here for INVERT_ENABLE
* for the time being since INVERT_ENABLE only applies to clocks enabled by
* CM_CLKEN_PLL
*/
static void omap2_clk_wait_ready(struct clk *clk) static void omap2_clk_wait_ready(struct clk *clk)
{ {
void __iomem *reg, *other_reg, *st_reg; void __iomem *reg, *other_reg, *st_reg;
...@@ -224,7 +229,10 @@ int _omap2_clk_enable(struct clk *clk) ...@@ -224,7 +229,10 @@ int _omap2_clk_enable(struct clk *clk)
} }
regval32 = cm_read_reg(clk->enable_reg); regval32 = cm_read_reg(clk->enable_reg);
regval32 |= (1 << clk->enable_bit); if (clk->flags & INVERT_ENABLE)
regval32 &= ~(1 << clk->enable_bit);
else
regval32 |= (1 << clk->enable_bit);
cm_write_reg(regval32, clk->enable_reg); cm_write_reg(regval32, clk->enable_reg);
wmb(); wmb();
...@@ -257,7 +265,10 @@ void _omap2_clk_disable(struct clk *clk) ...@@ -257,7 +265,10 @@ void _omap2_clk_disable(struct clk *clk)
} }
regval32 = cm_read_reg(clk->enable_reg); regval32 = cm_read_reg(clk->enable_reg);
regval32 &= ~(1 << clk->enable_bit); if (clk->flags & INVERT_ENABLE)
regval32 |= (1 << clk->enable_bit);
else
regval32 &= ~(1 << clk->enable_bit);
cm_write_reg(regval32, clk->enable_reg); cm_write_reg(regval32, clk->enable_reg);
wmb(); wmb();
} }
...@@ -709,10 +720,12 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) ...@@ -709,10 +720,12 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
#ifdef CONFIG_OMAP_RESET_CLOCKS #ifdef CONFIG_OMAP_RESET_CLOCKS
void __init omap2_clk_disable_unused(struct clk *clk) void __init omap2_clk_disable_unused(struct clk *clk)
{ {
u32 regval32; u32 regval32, v;
v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
regval32 = cm_read_reg(clk->enable_reg); regval32 = cm_read_reg(clk->enable_reg);
if ((regval32 & (1 << clk->enable_bit)) == 0) if ((regval32 & (1 << clk->enable_bit)) == v)
return; return;
printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
......
...@@ -104,7 +104,8 @@ extern void clk_enable_init_clocks(void); ...@@ -104,7 +104,8 @@ extern void clk_enable_init_clocks(void);
#define DELAYED_APP (1 << 9) /* Delay application of clock */ #define DELAYED_APP (1 << 9) /* Delay application of clock */
#define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
/* bits 12-20 are currently free */ #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
/* bits 13-20 are currently free */
#define CLOCK_IN_OMAP310 (1 << 21) #define CLOCK_IN_OMAP310 (1 << 21)
#define CLOCK_IN_OMAP730 (1 << 22) #define CLOCK_IN_OMAP730 (1 << 22)
#define CLOCK_IN_OMAP1510 (1 << 23) #define CLOCK_IN_OMAP1510 (1 << 23)
......
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