RealView: Move the SMP-specific initialisation out of __v6_setup

This patch moves the SCU initialisation and SMP/nAMP mode setting from
__v6_setup the the smp_prepare_cpus() and platform_secondary_init()
files as they rely on platform-specific settings.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

arch/arm/kernel/smp.c

@@ -341,6 +341,7 @@ void __init smp_prepare_boot_cpu(void)
 	unsigned int cpu = smp_processor_id();
 
 	per_cpu(cpu_data, cpu).idle = current;
+	cpu_smp_enable(cpu);
 }
 
 static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg)

arch/arm/mach-realview/platsmp.c

@@ -15,11 +15,13 @@
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
-#include <asm/hardware/arm_scu.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
+#include <asm/arch/board-eb.h>
+#include <asm/arch/scu.h>
+
 extern void realview_secondary_startup(void);
 
 /*
@@ -41,6 +43,38 @@ static unsigned int __init get_core_count(void)
 	return ncores;
 }
 
+/*
+ * Setup the SCU
+ */
+static void scu_enable(void)
+{
+	u32 scu_ctrl;
+
+	scu_ctrl = readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CTRL);
+	scu_ctrl |= 1;
+	writel(scu_ctrl, __io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CTRL);
+}
+
+/*
+ * Enable the SMP/nAMP mode for the CPU
+ */
+void cpu_smp_enable(unsigned int cpu)
+{
+	register u32 aux_ctrl;
+	unsigned long flags;
+
+	if (machine_is_realview_eb() && core_tile_eb11mp()) {
+		local_irq_save(flags);
+		flush_cache_all();
+		asm __volatile__(
+			"mrc	p15, 0, %0, c1, c0, 1\n"
+			"orr	%0, %0, #0x20\n"
+			"mcr	p15, 0, %0, c1, c0, 1\n"
+			: "=r" (aux_ctrl));
+		local_irq_restore(flags);
+	}
+}
+
 static DEFINE_SPINLOCK(boot_lock);
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
@@ -52,6 +86,11 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 	 */
 	smp_cross_call_done(cpumask_of_cpu(cpu));
 
+	/*
+	 * Enable the SMP/nAMP mode
+	 */
+	cpu_smp_enable(cpu);
+
 	/*
 	 * if any interrupts are already enabled for the primary
 	 * core (e.g. timer irq), then they will not have been enabled
@@ -210,11 +249,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 		cpu_set(i, cpu_present_map);
 
 	/*
-	 * Do we need any more CPUs? If so, then let them know where
-	 * to start. Note that, on modern versions of MILO, the "poke"
-	 * doesn't actually do anything until each individual core is
-	 * sent a soft interrupt to get it out of WFI
+	 * Initialise the SCU if there are more than one CPU and let
+	 * them know where to start. Note that, on modern versions of
+	 * MILO, the "poke" doesn't actually do anything until each
+	 * individual core is sent a soft interrupt to get it out of
+	 * WFI
 	 */
-	if (max_cpus > 1)
+	if (max_cpus > 1) {
+		scu_enable();
 		poke_milo();
+	}
 }

arch/arm/mm/proc-v6.S

@@ -17,10 +17,6 @@
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
-#ifdef CONFIG_SMP
-#include <asm/hardware/arm_scu.h>
-#endif
-
 #include "proc-macros.S"
 
 #define D_CACHE_LINE_SIZE	32
@@ -186,22 +182,6 @@ cpu_v6_name:
  *	- cache type register is implemented
  */
 __v6_setup:
-#ifdef CONFIG_SMP
-	/* Set up the SCU on core 0 only */
-	mrc	p15, 0, r0, c0, c0, 5		@ CPU core number
-	ands	r0, r0, #15
-	ldreq	r0, =SCU_BASE
-	ldreq	r5, [r0, #SCU_CTRL]
-	orreq	r5, r5, #1
-	streq	r5, [r0, #SCU_CTRL]
-
-#ifndef CONFIG_CPU_DCACHE_DISABLE
-	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
-	orr	r0, r0, #0x20
-	mcr	p15, 0, r0, c1, c0, 1
-#endif
-#endif
-
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c14, 0		@ clean+invalidate D cache
 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache

include/asm-arm/arch-realview/scu.h

 #ifndef __ASMARM_ARCH_SCU_H
 #define __ASMARM_ARCH_SCU_H
 
-#include <asm/arch/board-eb.h>
-
-#define SCU_BASE	REALVIEW_EB11MP_SCU_BASE
+/*
+ * SCU registers
+ */
+#define SCU_CTRL		0x00
+#define SCU_CONFIG		0x04
+#define SCU_CPU_STATUS		0x08
+#define SCU_INVALIDATE		0x0c
+#define SCU_FPGA_REVISION	0x10
 
 #endif

include/asm-arm/hardware/arm_scu.h

-#ifndef ASMARM_HARDWARE_ARM_SCU_H
-#define ASMARM_HARDWARE_ARM_SCU_H
-
-#include <asm/arch/scu.h>
-
-/*
- * SCU registers
- */
-#define SCU_CTRL		0x00
-#define SCU_CONFIG		0x04
-#define SCU_CPU_STATUS		0x08
-#define SCU_INVALIDATE		0x0c
-#define SCU_FPGA_REVISION	0x10
-
-#endif

include/asm-arm/smp.h

@@ -82,6 +82,11 @@ asmlinkage void secondary_start_kernel(void);
  */
 extern void platform_secondary_init(unsigned int cpu);
 
+/*
+ * Set up the CPU for SMP mode.
+ */
+extern void cpu_smp_enable(unsigned int cpu);
+
 /*
  * Initial data for bringing up a secondary CPU.
  */