Commit a63ad325 authored by Hans Verkuil's avatar Hans Verkuil Committed by Mauro Carvalho Chehab

V4L/DVB (5119): Various cx2341x documentation updates/fixes.

Signed-off-by: default avatarHans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@infradead.org>
parent 5cc1dd8c
...@@ -22,6 +22,8 @@ urged to choose a smaller block size and learn the scatter-gather technique. ...@@ -22,6 +22,8 @@ urged to choose a smaller block size and learn the scatter-gather technique.
Mailbox #10 is reserved for DMA transfer information. Mailbox #10 is reserved for DMA transfer information.
Note: the hardware expects little-endian data ('intel format').
Flow Flow
==== ====
...@@ -64,7 +66,7 @@ addresses are the physical memory location of the target DMA buffer. ...@@ -64,7 +66,7 @@ addresses are the physical memory location of the target DMA buffer.
Each S-G array element is a struct of three 32-bit words. The first word is Each S-G array element is a struct of three 32-bit words. The first word is
the source address, the second is the destination address. Both take up the the source address, the second is the destination address. Both take up the
entire 32 bits. The lowest 16 bits of the third word is the transfer byte entire 32 bits. The lowest 18 bits of the third word is the transfer byte
count. The high-bit of the third word is the "last" flag. The last-flag tells count. The high-bit of the third word is the "last" flag. The last-flag tells
the card to raise the DMA_DONE interrupt. From hard personal experience, if the card to raise the DMA_DONE interrupt. From hard personal experience, if
you forget to set this bit, the card will still "work" but the stream will you forget to set this bit, the card will still "work" but the stream will
...@@ -78,8 +80,8 @@ Array Element: ...@@ -78,8 +80,8 @@ Array Element:
- 32-bit Source Address - 32-bit Source Address
- 32-bit Destination Address - 32-bit Destination Address
- 16-bit reserved (high bit is the last flag) - 14-bit reserved (high bit is the last flag)
- 16-bit byte count - 18-bit byte count
DMA Transfer Status DMA Transfer Status
=================== ===================
...@@ -87,8 +89,8 @@ DMA Transfer Status ...@@ -87,8 +89,8 @@ DMA Transfer Status
Register 0x0004 holds the DMA Transfer Status: Register 0x0004 holds the DMA Transfer Status:
Bit Bit
4 Scatter-Gather array error
3 DMA write error
2 DMA read error
1 write completed
0 read completed 0 read completed
1 write completed
2 DMA read error
3 DMA write error
4 Scatter-Gather array error
...@@ -498,12 +498,14 @@ Name CX2341X_ENC_GET_PREV_DMA_INFO_MB_9 ...@@ -498,12 +498,14 @@ Name CX2341X_ENC_GET_PREV_DMA_INFO_MB_9
Enum 203/0xCB Enum 203/0xCB
Description Description
Returns information on the previous DMA transfer in conjunction with Returns information on the previous DMA transfer in conjunction with
bit 27 of the interrupt mask. Uses mailbox 9. bit 27 or 18 of the interrupt mask. Uses mailbox 9.
Result[0] Result[0]
Status bits: Status bits:
Bit 0 set indicates transfer complete 0 read completed
Bit 2 set indicates transfer error 1 write completed
Bit 4 set indicates linked list error 2 DMA read error
3 DMA write error
4 Scatter-Gather array error
Result[1] Result[1]
DMA type DMA type
Result[2] Result[2]
......
This document describes the cx2341x memory map and documents some of the register This document describes the cx2341x memory map and documents some of the register
space. space.
Note: the memory long words are little-endian ('intel format').
Warning! This information was figured out from searching through the memory and Warning! This information was figured out from searching through the memory and
registers, this information may not be correct and is certainly not complete, and registers, this information may not be correct and is certainly not complete, and
was not derived from anything more than searching through the memory space with was not derived from anything more than searching through the memory space with
...@@ -67,7 +69,7 @@ DMA Registers 0x000-0xff: ...@@ -67,7 +69,7 @@ DMA Registers 0x000-0xff:
0x84 - first write linked list reg, for pci memory addr 0x84 - first write linked list reg, for pci memory addr
0x88 - first write linked list reg, for length of buffer in memory addr 0x88 - first write linked list reg, for length of buffer in memory addr
(|0x80000000 or this for last link) (|0x80000000 or this for last link)
0x8c-0xcc - rest of write linked list reg, 8 sets of 3 total, DMA goes here 0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
from linked list addr in reg 0x0c, firmware must push through or from linked list addr in reg 0x0c, firmware must push through or
something. something.
0xe0 - first (and only) read linked list reg, for pci memory addr 0xe0 - first (and only) read linked list reg, for pci memory addr
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment