Commit a536efcc authored by Mithlesh Thukral's avatar Mithlesh Thukral Committed by Greg Kroah-Hartman

Staging: sxg: Add Rev B support in the Sahara SXG driver

This patch makes the Sahara SXG driver use Rev B firmware instead of Rev A.
The firmware version is 1.71
Signed-off-by: default avatarMichael Miles <mmiles@alacritech.com>
Signed-off-by: default avatarMithlesh Thukral <mithlesh@linsyssoft.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 497ef3c5
This diff is collapsed.
...@@ -369,9 +369,9 @@ enum SXG_LINK_STATE { ...@@ -369,9 +369,9 @@ enum SXG_LINK_STATE {
/* Microcode file selection codes */ /* Microcode file selection codes */
enum SXG_UCODE_SEL { enum SXG_UCODE_SEL {
SXG_UCODE_SAHARA, /* Sahara ucode */ SXG_UCODE_SYSTEM, /* System (operational) uucode */
SXG_UCODE_SDIAGCPU, /* Sahara CPU diagnostic ucode */ SXG_UCODE_SDIAGCPU, /* System CPU diagnostic ucode */
SXG_UCODE_SDIAGSYS /* Sahara system diagnostic ucode */ SXG_UCODE_SDIAGSYS /* System diagnostic ucode */
}; };
...@@ -537,6 +537,7 @@ struct adapter_t { ...@@ -537,6 +537,7 @@ struct adapter_t {
u32 memorylength; u32 memorylength;
u32 drambase; u32 drambase;
u32 dramlength; u32 dramlength;
enum asic_type asictype; /* type of ASIC (chip) */
unsigned int activated; unsigned int activated;
u32 intrregistered; u32 intrregistered;
unsigned int isp_initialized; unsigned int isp_initialized;
...@@ -680,6 +681,8 @@ struct adapter_t { ...@@ -680,6 +681,8 @@ struct adapter_t {
u32 RssEnabled:1; /* RSS Enabled */ u32 RssEnabled:1; /* RSS Enabled */
u32 FailOnBadEeprom:1; /* Fail on Bad Eeprom */ u32 FailOnBadEeprom:1; /* Fail on Bad Eeprom */
u32 DiagStart:1; /* Init adapter for diagnostic start */ u32 DiagStart:1; /* Init adapter for diagnostic start */
u32 XmtFcEnabled:1;
u32 RcvFcEnabled:1;
/* Stats */ /* Stats */
u32 PendingRcvCount; /* Outstanding rcv indications */ u32 PendingRcvCount; /* Outstanding rcv indications */
u32 PendingXmtCount; /* Outstanding send requests */ u32 PendingXmtCount; /* Outstanding send requests */
......
...@@ -150,13 +150,16 @@ struct sxg_ucode_regs { ...@@ -150,13 +150,16 @@ struct sxg_ucode_regs {
/* Disable interrupt aggregation on xmt */ /* Disable interrupt aggregation on xmt */
#define SXG_AGG_XMT_DISABLE 0x80000000 #define SXG_AGG_XMT_DISABLE 0x80000000
/* The Microcode supports up to 8 RSS queues */ /* The Microcode supports up to 16 RSS queues (RevB) */
#define SXG_MAX_RSS 8 #define SXG_MAX_RSS 16
#define SXG_MAX_RSS_REVA 8
#define SXG_MAX_RSS_TABLE_SIZE 256 /* 256-byte max */ #define SXG_MAX_RSS_TABLE_SIZE 256 /* 256-byte max */
#define SXG_RSS_TCP6 0x00000001 /* RSS TCP over IPv6 */ #define SXG_RSS_REVA_TCP6 0x00000001 /* RSS TCP over IPv6 */
#define SXG_RSS_TCP4 0x00000002 /* RSS TCP over IPv4 */ #define SXG_RSS_REVA_TCP4 0x00000002 /* RSS TCP over IPv4 */
#define SXG_RSS_IP 0x00000001 /* RSS TCP over IPv6 */
#define SXG_RSS_TCP 0x00000002 /* RSS TCP over IPv4 */
#define SXG_RSS_LEGACY 0x00000004 /* Line-base interrupts */ #define SXG_RSS_LEGACY 0x00000004 /* Line-base interrupts */
#define SXG_RSS_TABLE_SIZE 0x0000FF00 /* Table size mask */ #define SXG_RSS_TABLE_SIZE 0x0000FF00 /* Table size mask */
......
...@@ -18,6 +18,22 @@ ...@@ -18,6 +18,22 @@
/* PCI Device ID */ /* PCI Device ID */
#define SXG_DEVICE_ID 0x0009 /* Sahara Device ID */ #define SXG_DEVICE_ID 0x0009 /* Sahara Device ID */
/* Type of ASIC in use */
enum asic_type {
SAHARA_REV_A,
SAHARA_REV_B
};
/* Type of Xcvr in fiber card */
enum xcvr_type {
XCVR_UNKNOWN,
XCVR_NONE,
XCVR_SR,
XCVR_LR,
XCVR_LRM,
XCVR_CR
};
/* /*
* Subsystem IDs. * Subsystem IDs.
* *
...@@ -265,9 +281,11 @@ struct sxg_hw_regs { ...@@ -265,9 +281,11 @@ struct sxg_hw_regs {
#define RCV_CONFIG_HASH_4 0x00020000 /* Hash depth 4 */ #define RCV_CONFIG_HASH_4 0x00020000 /* Hash depth 4 */
#define RCV_CONFIG_HASH_2 0x00030000 /* Hash depth 2 */ #define RCV_CONFIG_HASH_2 0x00030000 /* Hash depth 2 */
/* Buffer length bits 15:4. ie multiple of 16. */ /* Buffer length bits 15:4. ie multiple of 16. */
#define RCV_CONFIG_BUFLEN_MASK 0x0000FFF0 #define RCV_CONFIG_BUFLEN_MASK 0x0000FFE0
/* Disable socket detection on attn */ /* Disable socket detection on attn */
#define RCV_CONFIG_SKT_DIS 0x00000008 #define RCV_CONFIG_SKT_DIS 0x00000008
#define RCV_CONFIG_HIPRICTL 0x00000002 /* Ctrl frames on high-prioirty RcvQ */
#define RCV_CONFIG_NEWSTATUSFMT 0x00000001 /* Use RevB status format */
/* /*
* Macro to determine RCV_CONFIG_BUFLEN based on maximum frame size. * Macro to determine RCV_CONFIG_BUFLEN based on maximum frame size.
* We add 18 bytes for Sahara receive status and padding, plus 4 bytes for CRC, * We add 18 bytes for Sahara receive status and padding, plus 4 bytes for CRC,
...@@ -640,6 +658,9 @@ struct sxg_hw_regs { ...@@ -640,6 +658,9 @@ struct sxg_hw_regs {
/* PHY_XS_LANE_STATUS register bit definitions */ /* PHY_XS_LANE_STATUS register bit definitions */
#define XS_LANE_ALIGN 0x1000 /* XS transmit lanes aligned */ #define XS_LANE_ALIGN 0x1000 /* XS transmit lanes aligned */
#define XCVR_VENDOR_LEN 16 /* xcvr vendor len */
#define XCVR_MODEL_LEN 16 /* xcvr model len */
/* PHY Microcode download data structure */ /* PHY Microcode download data structure */
struct phy_ucode { struct phy_ucode {
ushort Addr; ushort Addr;
...@@ -970,6 +991,10 @@ struct adapt_userinfo { ...@@ -970,6 +991,10 @@ struct adapt_userinfo {
/* u32 LinkState; */ /* u32 LinkState; */
u32 LinkSpeed; /* not currently needed */ u32 LinkSpeed; /* not currently needed */
u32 LinkDuplex; /* not currently needed */ u32 LinkDuplex; /* not currently needed */
enum xcvr_type XcvrType; /* type of xcvr on fiber card */
/* fiber card xcvr vendor */
unsigned char XcvrVendor[XCVR_VENDOR_LEN];
unsigned char XcvrMode[XCVR_MODEL_LEN];
u32 Port; /* not currently needed */ u32 Port; /* not currently needed */
u32 PhysPort; /* not currently needed */ u32 PhysPort; /* not currently needed */
ushort PciLanes; ushort PciLanes;
...@@ -984,11 +1009,7 @@ struct adapt_userinfo { ...@@ -984,11 +1009,7 @@ struct adapt_userinfo {
/* Miscellaneous Hardware definitions */ /* Miscellaneous Hardware definitions */
/* Type of ASIC in use */ /* Hardware Type definitions */
enum ASIC_TYPE{
SAHARA_REV_A,
SAHARA_REV_B
};
/* Sahara (ASIC level) defines */ /* Sahara (ASIC level) defines */
#define SAHARA_GRAM_SIZE 0x020000 /* GRAM size - 128 KB */ #define SAHARA_GRAM_SIZE 0x020000 /* GRAM size - 128 KB */
......
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