This patch adds 4-bit ECC support for large page NAND chips using the new

ECC mode NAND_ECC_HW_OOB_FIRST.  The platform data from board-dm355-evm
has been adjusted to use this mode.

The patches have been verified on DM355 device with 2K Micron devices
using mtd-tests and JFFS2.  Error correction upto 4-bits has also been
verified using nandwrite/nanddump utilities.

This patch series applies to linux-mtd next (mmotm) GIT tree.

This version (v4) addresses the review comment to leave 2 bytes at offset
0 for NAND manufacturer badblock markers.

Cc: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>

drivers/mtd/nand/davinci_nand.c

@@ -522,8 +522,8 @@ static struct nand_ecclayout hwecc4_2048 __initconst = {
 		54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
 		},
 	.oobfree = {
-		/* 1 byte at offset 0 holds manufacturer badblock marker */
-		{.offset = 1, .length = 23, },
+		/* 2 bytes at offset 0 hold manufacturer badblock markers */
+		{.offset = 2, .length = 22, },
 		/* 5 bytes at offset 8 hold BBT markers */
 		/* 8 bytes at offset 16 hold JFFS2 clean markers */
 	},