Commit 9db95cb6 authored by Haojian Zhuang's avatar Haojian Zhuang Committed by Eric Miao

[ARM] pxa: expand irq support for PXA93x and PXA950

PXA93x/950 has additional 64 GPIOs, each is a secondary interrupt
source for IRQ_GPIO_2_x, extend PXA_GPIO_IRQ_{BASE,NUM}.

PXA93x/950 specific IRQ definitions are added as well.
Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: default avatarEric Miao <eric.y.miao@gmail.com>
parent 063936df
......@@ -68,6 +68,7 @@
#ifdef CONFIG_PXA3xx
#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */
#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */
#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */
#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */
#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */
#define IRQ_GRPHICS PXA_IRQ(39) /* Graphics Controller */
......@@ -81,8 +82,31 @@
#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
#endif
#define PXA_GPIO_IRQ_BASE PXA_IRQ(64)
#define PXA_GPIO_IRQ_NUM (128)
#ifdef CONFIG_CPU_PXA935
#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */
#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */
#define IRQ_MMC3_PXA935 PXA_IRQ(72) /* MMC3 Controller (PXA935) */
#define IRQ_MMC4_PXA935 PXA_IRQ(73) /* MMC4 Controller (PXA935) */
#define IRQ_MMC5_PXA935 PXA_IRQ(74) /* MMC5 Controller (PXA935) */
#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */
#endif
#ifdef CONFIG_CPU_PXA930
#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */
#define IRQ_ACIPC0 PXA_IRQ(5)
#define IRQ_ACIPC1 PXA_IRQ(40)
#define IRQ_ACIPC2 PXA_IRQ(19)
#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball */
#endif
#ifdef CONFIG_CPU_PXA950
#define IRQ_GC500 PXA_IRQ(70) /* Graphics Controller (PXA950) */
#endif
#define PXA_GPIO_IRQ_BASE PXA_IRQ(96)
#define PXA_GPIO_IRQ_NUM (192)
#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
......
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