sh: Fix up the SH-5 build with caches enabled.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

arch/sh/include/asm/system.h

@@ -14,18 +14,6 @@
 
 #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
 
-#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
-#define __icbi()			\
-{					\
-	unsigned long __addr;		\
-	__addr = 0xa8000000;		\
-	__asm__ __volatile__(		\
-		"icbi   %0\n\t"		\
-		: /* no output */	\
-		: "m" (__m(__addr)));	\
-}
-#endif
-
 /*
  * A brief note on ctrl_barrier(), the control register write barrier.
  *
@@ -44,7 +32,7 @@
 #define mb()		__asm__ __volatile__ ("synco": : :"memory")
 #define rmb()		mb()
 #define wmb()		__asm__ __volatile__ ("synco": : :"memory")
-#define ctrl_barrier()	__icbi()
+#define ctrl_barrier()	__icbi(0xa8000000)
 #define read_barrier_depends()	do { } while(0)
 #else
 #define mb()		__asm__ __volatile__ ("": : :"memory")

arch/sh/include/asm/system_32.h

@@ -63,6 +63,16 @@ do {									\
 #define __restore_dsp(tsk)	do { } while (0)
 #endif
 
+#if defined(CONFIG_CPU_SH4A)
+#define __icbi(addr)	__asm__ __volatile__ ( "icbi @%0\n\t" : : "r" (addr))
+#else
+#define __icbi(addr)	mb()
+#endif
+
+#define __ocbp(addr)	__asm__ __volatile__ ( "ocbp @%0\n\t" : : "r" (addr))
+#define __ocbi(addr)	__asm__ __volatile__ ( "ocbi @%0\n\t" : : "r" (addr))
+#define __ocbwb(addr)	__asm__ __volatile__ ( "ocbwb @%0\n\t" : : "r" (addr))
+
 struct task_struct *__switch_to(struct task_struct *prev,
 				struct task_struct *next);
 

arch/sh/include/asm/system_64.h

@@ -37,6 +37,11 @@ do {								\
 #define jump_to_uncached()	do { } while (0)
 #define back_to_cached()	do { } while (0)
 
+#define __icbi(addr)	__asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
+#define __ocbp(addr)	__asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
+#define __ocbi(addr)	__asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
+#define __ocbwb(addr)	__asm__ __volatile__ ( "ocbwb %0, 0\n\t" : : "r" (addr))
+
 static inline reg_size_t register_align(void *val)
 {
 	return (unsigned long long)(signed long long)(signed long)val;

arch/sh/kernel/sh_ksyms_64.c

@@ -30,14 +30,6 @@ extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
 EXPORT_SYMBOL(dump_fpu);
 EXPORT_SYMBOL(kernel_thread);
 
-#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU)
-EXPORT_SYMBOL(clear_user_page);
-#endif
-
-#ifndef CONFIG_CACHE_OFF
-EXPORT_SYMBOL(flush_dcache_page);
-#endif
-
 #ifdef CONFIG_VT
 EXPORT_SYMBOL(screen_info);
 #endif

arch/sh/mm/flush-sh4.c

@@ -19,28 +19,19 @@ static void sh4__flush_wback_region(void *start, int size)
 	cnt = (end - v) / L1_CACHE_BYTES;
 
 	while (cnt >= 8) {
-		asm volatile("ocbwb	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbwb	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbwb	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbwb	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbwb	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbwb	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbwb	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbwb	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
+		__ocbwb(v); v += L1_CACHE_BYTES;
+		__ocbwb(v); v += L1_CACHE_BYTES;
+		__ocbwb(v); v += L1_CACHE_BYTES;
+		__ocbwb(v); v += L1_CACHE_BYTES;
+		__ocbwb(v); v += L1_CACHE_BYTES;
+		__ocbwb(v); v += L1_CACHE_BYTES;
+		__ocbwb(v); v += L1_CACHE_BYTES;
+		__ocbwb(v); v += L1_CACHE_BYTES;
 		cnt -= 8;
 	}
 
 	while (cnt) {
-		asm volatile("ocbwb	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
+		__ocbwb(v); v += L1_CACHE_BYTES;
 		cnt--;
 	}
 }
@@ -62,27 +53,18 @@ static void sh4__flush_purge_region(void *start, int size)
 	cnt = (end - v) / L1_CACHE_BYTES;
 
 	while (cnt >= 8) {
-		asm volatile("ocbp	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbp	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbp	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbp	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbp	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbp	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbp	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbp	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
+		__ocbp(v); v += L1_CACHE_BYTES;
+		__ocbp(v); v += L1_CACHE_BYTES;
+		__ocbp(v); v += L1_CACHE_BYTES;
+		__ocbp(v); v += L1_CACHE_BYTES;
+		__ocbp(v); v += L1_CACHE_BYTES;
+		__ocbp(v); v += L1_CACHE_BYTES;
+		__ocbp(v); v += L1_CACHE_BYTES;
+		__ocbp(v); v += L1_CACHE_BYTES;
 		cnt -= 8;
 	}
 	while (cnt) {
-		asm volatile("ocbp	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
+		__ocbp(v); v += L1_CACHE_BYTES;
 		cnt--;
 	}
 }
@@ -101,28 +83,19 @@ static void sh4__flush_invalidate_region(void *start, int size)
 	cnt = (end - v) / L1_CACHE_BYTES;
 
 	while (cnt >= 8) {
-		asm volatile("ocbi	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbi	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbi	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbi	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbi	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbi	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbi	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
-		asm volatile("ocbi	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
+		__ocbi(v); v += L1_CACHE_BYTES;
+		__ocbi(v); v += L1_CACHE_BYTES;
+		__ocbi(v); v += L1_CACHE_BYTES;
+		__ocbi(v); v += L1_CACHE_BYTES;
+		__ocbi(v); v += L1_CACHE_BYTES;
+		__ocbi(v); v += L1_CACHE_BYTES;
+		__ocbi(v); v += L1_CACHE_BYTES;
+		__ocbi(v); v += L1_CACHE_BYTES;
 		cnt -= 8;
 	}
 
 	while (cnt) {
-		asm volatile("ocbi	@%0" : : "r" (v));
-		v += L1_CACHE_BYTES;
+		__ocbi(v); v += L1_CACHE_BYTES;
 		cnt--;
 	}
 }