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linux-davinci
Commit 857355a7 authored by Kevin Hilman's avatar Kevin Hilman
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Merge ../../omap/pristine

parents c0eb8cfa 84e28a20
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Showing with 120 additions and 120 deletions
drivers/usb/musb/g_ep0.c
View file @ 857355a7
......@@ -58,12 +58,12 @@
static char *decode_ep0stage(u8 stage)
{
switch(stage) {
case MGC_END0_STAGE_SETUP: return "idle";
case MGC_END0_STAGE_TX: return "in";
case MGC_END0_STAGE_RX: return "out";
case MGC_END0_STAGE_ACKWAIT: return "wait";
case MGC_END0_STAGE_STATUSIN: return "in/status";
case MGC_END0_STAGE_STATUSOUT: return "out/status";
case MUSB_EP0_STAGE_SETUP: return "idle";
case MUSB_EP0_STAGE_TX: return "in";
case MUSB_EP0_STAGE_RX: return "out";
case MUSB_EP0_STAGE_ACKWAIT: return "wait";
case MUSB_EP0_STAGE_STATUSIN: return "in/status";
case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
default: return "?";
}
}
......@@ -197,7 +197,7 @@ service_in_request(struct musb *musb,
*/
static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
{
musb->ep0_state = MGC_END0_STAGE_SETUP;
musb->ep0_state = MUSB_EP0_STAGE_SETUP;
musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
}
......@@ -459,7 +459,7 @@ static void ep0_rxstate(struct musb *this)
req->actual += tmp;
tmp = MUSB_CSR0_P_SVDRXPKTRDY;
if (tmp < 64 || req->actual == req->length) {
this->ep0_state = MGC_END0_STAGE_STATUSIN;
this->ep0_state = MUSB_EP0_STAGE_STATUSIN;
tmp |= MUSB_CSR0_P_DATAEND;
} else
req = NULL;
......@@ -506,7 +506,7 @@ static void ep0_txstate(struct musb *musb)
/* update the flags */
if (fifo_count < MUSB_MAX_END0_PACKET
|| request->actual == request->length) {
musb->ep0_state = MGC_END0_STAGE_STATUSOUT;
musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
csr |= MUSB_CSR0_P_DATAEND;
} else
request = NULL;
......@@ -565,16 +565,16 @@ musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
if (req->wLength == 0) {
if (req->bRequestType & USB_DIR_IN)
musb->ackpend |= MUSB_CSR0_TXPKTRDY;
musb->ep0_state = MGC_END0_STAGE_ACKWAIT;
musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
} else if (req->bRequestType & USB_DIR_IN) {
musb->ep0_state = MGC_END0_STAGE_TX;
musb->ep0_state = MUSB_EP0_STAGE_TX;
musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
while ((musb_readw(regs, MUSB_CSR0)
& MUSB_CSR0_RXPKTRDY) != 0)
cpu_relax();
musb->ackpend = 0;
} else
musb->ep0_state = MGC_END0_STAGE_RX;
musb->ep0_state = MUSB_EP0_STAGE_RX;
}
static int
......@@ -619,7 +619,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
musb_writew(regs, MUSB_CSR0,
csr & ~MUSB_CSR0_P_SENTSTALL);
retval = IRQ_HANDLED;
musb->ep0_state = MGC_END0_STAGE_SETUP;
musb->ep0_state = MUSB_EP0_STAGE_SETUP;
csr = musb_readw(regs, MUSB_CSR0);
}
......@@ -627,7 +627,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
if (csr & MUSB_CSR0_P_SETUPEND) {
musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
retval = IRQ_HANDLED;
musb->ep0_state = MGC_END0_STAGE_SETUP;
musb->ep0_state = MUSB_EP0_STAGE_SETUP;
csr = musb_readw(regs, MUSB_CSR0);
/* NOTE: request may need completion */
}
......@@ -638,7 +638,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
*/
switch (musb->ep0_state) {
case MGC_END0_STAGE_TX:
case MUSB_EP0_STAGE_TX:
/* irq on clearing txpktrdy */
if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
ep0_txstate(musb);
......@@ -646,7 +646,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
}
break;
case MGC_END0_STAGE_RX:
case MUSB_EP0_STAGE_RX:
/* irq on set rxpktrdy */
if (csr & MUSB_CSR0_RXPKTRDY) {
ep0_rxstate(musb);
......@@ -654,7 +654,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
}
break;
case MGC_END0_STAGE_STATUSIN:
case MUSB_EP0_STAGE_STATUSIN:
/* end of sequence #2 (OUT/RX state) or #3 (no data) */
/* update address (if needed) only @ the end of the
......@@ -679,7 +679,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
}
/* FALLTHROUGH */
case MGC_END0_STAGE_STATUSOUT:
case MUSB_EP0_STAGE_STATUSOUT:
/* end of sequence #1: write to host (TX state) */
{
struct usb_request *req;
......@@ -689,10 +689,10 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
musb_g_ep0_giveback(musb, req);
}
retval = IRQ_HANDLED;
musb->ep0_state = MGC_END0_STAGE_SETUP;
musb->ep0_state = MUSB_EP0_STAGE_SETUP;
/* FALLTHROUGH */
case MGC_END0_STAGE_SETUP:
case MUSB_EP0_STAGE_SETUP:
if (csr & MUSB_CSR0_RXPKTRDY) {
struct usb_ctrlrequest setup;
int handled = 0;
......@@ -724,7 +724,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
* device/endpoint feature set/clear operations)
* plus SET_CONFIGURATION and others we must
*/
case MGC_END0_STAGE_ACKWAIT:
case MUSB_EP0_STAGE_ACKWAIT:
handled = service_zero_data_request(
musb, &setup);
......@@ -732,7 +732,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
if (handled > 0) {
musb->ackpend |= MUSB_CSR0_P_DATAEND;
musb->ep0_state =
MGC_END0_STAGE_STATUSIN;
MUSB_EP0_STAGE_STATUSIN;
}
break;
......@@ -740,18 +740,18 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
* requests that we can't forward, GET_DESCRIPTOR
* and others that we must
*/
case MGC_END0_STAGE_TX:
case MUSB_EP0_STAGE_TX:
handled = service_in_request(musb, &setup);
if (handled > 0) {
musb->ackpend = MUSB_CSR0_TXPKTRDY
| MUSB_CSR0_P_DATAEND;
musb->ep0_state =
MGC_END0_STAGE_STATUSOUT;
MUSB_EP0_STAGE_STATUSOUT;
}
break;
/* sequence #2 (OUT from host), always forward */
default: /* MGC_END0_STAGE_RX */
default: /* MUSB_EP0_STAGE_RX */
break;
}
......@@ -774,7 +774,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
stall:
DBG(3, "stall (%d)\n", handled);
musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
musb->ep0_state = MGC_END0_STAGE_SETUP;
musb->ep0_state = MUSB_EP0_STAGE_SETUP;
finish:
musb_writew(regs, MUSB_CSR0,
musb->ackpend);
......@@ -783,7 +783,7 @@ finish:
}
break;
case MGC_END0_STAGE_ACKWAIT:
case MUSB_EP0_STAGE_ACKWAIT:
/* This should not happen. But happens with tusb6010 with
* g_file_storage and high speed. Do nothing.
*/
......@@ -794,7 +794,7 @@ finish:
/* "can't happen" */
WARN_ON(1);
musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
musb->ep0_state = MGC_END0_STAGE_SETUP;
musb->ep0_state = MUSB_EP0_STAGE_SETUP;
break;
}
......@@ -846,9 +846,9 @@ musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
}
switch (musb->ep0_state) {
case MGC_END0_STAGE_RX: /* control-OUT data */
case MGC_END0_STAGE_TX: /* control-IN data */
case MGC_END0_STAGE_ACKWAIT: /* zero-length data */
case MUSB_EP0_STAGE_RX: /* control-OUT data */
case MUSB_EP0_STAGE_TX: /* control-IN data */
case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
status = 0;
break;
default:
......@@ -868,15 +868,15 @@ musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
musb_ep_select(musb->mregs, 0);
/* sequence #1, IN ... start writing the data */
if (musb->ep0_state == MGC_END0_STAGE_TX)
if (musb->ep0_state == MUSB_EP0_STAGE_TX)
ep0_txstate(musb);
/* sequence #3, no-data ... issue IN status */
else if (musb->ep0_state == MGC_END0_STAGE_ACKWAIT) {
else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
if (req->request.length)
status = -EINVAL;
else {
musb->ep0_state = MGC_END0_STAGE_STATUSIN;
musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
musb_writew(regs, MUSB_CSR0,
musb->ackpend | MUSB_CSR0_P_DATAEND);
musb->ackpend = 0;
......@@ -929,16 +929,16 @@ static int musb_g_ep0_halt(struct usb_ep *e, int value)
}
switch (musb->ep0_state) {
case MGC_END0_STAGE_TX: /* control-IN data */
case MGC_END0_STAGE_ACKWAIT: /* STALL for zero-length data */
case MGC_END0_STAGE_RX: /* control-OUT data */
case MUSB_EP0_STAGE_TX: /* control-IN data */
case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
case MUSB_EP0_STAGE_RX: /* control-OUT data */
status = 0;
musb_ep_select(base, 0);
csr = musb_readw(regs, MUSB_CSR0);
csr |= MUSB_CSR0_P_SENDSTALL;
musb_writew(regs, MUSB_CSR0, csr);
musb->ep0_state = MGC_END0_STAGE_SETUP;
musb->ep0_state = MUSB_EP0_STAGE_SETUP;
break;
default:
DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
......
drivers/usb/musb/musb_gadget.c
View file @ 857355a7
......@@ -1434,6 +1434,7 @@ static int musb_gadget_wakeup(struct usb_gadget *gadget)
status = 0;
goto done;
default:
DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
goto done;
}
......@@ -1931,7 +1932,7 @@ void musb_g_suspend(struct musb *musb)
}
}
/* Called during SRP. Caller must hold lock */
/* Called during SRP */
void musb_g_wakeup(struct musb *musb)
{
musb_gadget_wakeup(&musb->g);
......@@ -1961,6 +1962,8 @@ void musb_g_disconnect(struct musb *musb)
switch (musb->xceiv.state) {
default:
#ifdef CONFIG_USB_MUSB_OTG
DBG(2, "Unhandled disconnect %s, setting a_idle\n",
otg_state_string(musb));
musb->xceiv.state = OTG_STATE_A_IDLE;
break;
case OTG_STATE_A_PERIPHERAL:
......@@ -1970,6 +1973,7 @@ void musb_g_disconnect(struct musb *musb)
case OTG_STATE_B_HOST:
#endif
case OTG_STATE_B_PERIPHERAL:
case OTG_STATE_B_IDLE:
musb->xceiv.state = OTG_STATE_B_IDLE;
break;
case OTG_STATE_B_SRP_INIT:
......@@ -2015,7 +2019,7 @@ __acquires(musb->lock)
musb->is_suspended = 0;
MUSB_DEV_MODE(musb);
musb->address = 0;
musb->ep0_state = MGC_END0_STAGE_SETUP;
musb->ep0_state = MUSB_EP0_STAGE_SETUP;
musb->may_wakeup = 0;
musb->g.b_hnp_enable = 0;
......
drivers/usb/musb/musb_host.c
View file @ 857355a7
......@@ -189,7 +189,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
/* control transfers always start with SETUP */
is_in = 0;
hw_ep->out_qh = qh;
musb->ep0_stage = MGC_END0_START;
musb->ep0_stage = MUSB_EP0_START;
buf = urb->setup_packet;
len = 8;
break;
......@@ -953,7 +953,7 @@ static int musb_h_ep0_continue(struct musb *musb,
struct usb_ctrlrequest *request;
switch (musb->ep0_stage) {
case MGC_END0_IN:
case MUSB_EP0_IN:
fifo_dest = urb->transfer_buffer + urb->actual_length;
fifo_count = min(len, ((u16) (urb->transfer_buffer_length
- urb->actual_length)));
......@@ -971,7 +971,7 @@ static int musb_h_ep0_continue(struct musb *musb,
urb->transfer_buffer_length)
more = TRUE;
break;
case MGC_END0_START:
case MUSB_EP0_START:
request = (struct usb_ctrlrequest *) urb->setup_packet;
if (!request->wLength) {
......@@ -979,16 +979,16 @@ static int musb_h_ep0_continue(struct musb *musb,
break;
} else if (request->bRequestType & USB_DIR_IN) {
DBG(4, "start IN-DATA\n");
musb->ep0_stage = MGC_END0_IN;
musb->ep0_stage = MUSB_EP0_IN;
more = TRUE;
break;
} else {
DBG(4, "start OUT-DATA\n");
musb->ep0_stage = MGC_END0_OUT;
musb->ep0_stage = MUSB_EP0_OUT;
more = TRUE;
}
/* FALLTHROUGH */
case MGC_END0_OUT:
case MUSB_EP0_OUT:
fifo_count = min(qh->maxpacket, ((u16)
(urb->transfer_buffer_length
- urb->actual_length)));
......@@ -1043,7 +1043,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
csr, qh, len, urb, musb->ep0_stage);
/* if we just did status stage, we are done */
if (MGC_END0_STATUS == musb->ep0_stage) {
if (MUSB_EP0_STATUS == musb->ep0_stage) {
retval = IRQ_HANDLED;
complete = TRUE;
}
......@@ -1114,7 +1114,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
/* call common logic and prepare response */
if (musb_h_ep0_continue(musb, len, urb)) {
/* more packets required */
csr = (MGC_END0_IN == musb->ep0_stage)
csr = (MUSB_EP0_IN == musb->ep0_stage)
? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
} else {
/* data transfer complete; perform status phase */
......@@ -1127,7 +1127,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
| MUSB_CSR0_TXPKTRDY;
/* flag status stage */
musb->ep0_stage = MGC_END0_STATUS;
musb->ep0_stage = MUSB_EP0_STATUS;
DBG(5, "ep0 STATUS, csr %04x\n", csr);
......@@ -1135,7 +1135,7 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
musb_writew(epio, MUSB_CSR0, csr);
retval = IRQ_HANDLED;
} else
musb->ep0_stage = MGC_END0_IDLE;
musb->ep0_stage = MUSB_EP0_IDLE;
/* call completion handler if done */
if (complete)
......
drivers/usb/musb/musbdefs.h
View file @ 857355a7
......@@ -181,21 +181,21 @@ static inline void musb_host_rx(struct musb *m, u8 e) {}
/* host side ep0 states */
enum musb_h_ep0_state {
MGC_END0_IDLE,
MGC_END0_START, /* expect ack of setup */
MGC_END0_IN, /* expect IN DATA */
MGC_END0_OUT, /* expect ack of OUT DATA */
MGC_END0_STATUS, /* expect ack of STATUS */
MUSB_EP0_IDLE,
MUSB_EP0_START, /* expect ack of setup */
MUSB_EP0_IN, /* expect IN DATA */
MUSB_EP0_OUT, /* expect ack of OUT DATA */
MUSB_EP0_STATUS, /* expect ack of STATUS */
} __attribute__ ((packed));
/* peripheral side ep0 states */
enum musb_g_ep0_state {
MGC_END0_STAGE_SETUP, /* idle, waiting for setup */
MGC_END0_STAGE_TX, /* IN data */
MGC_END0_STAGE_RX, /* OUT data */
MGC_END0_STAGE_STATUSIN, /* (after OUT data) */
MGC_END0_STAGE_STATUSOUT, /* (after IN data) */
MGC_END0_STAGE_ACKWAIT, /* after zlp, before statusin */
MUSB_EP0_STAGE_SETUP, /* idle, waiting for setup */
MUSB_EP0_STAGE_TX, /* IN data */
MUSB_EP0_STAGE_RX, /* OUT data */
MUSB_EP0_STAGE_STATUSIN, /* (after OUT data) */
MUSB_EP0_STAGE_STATUSOUT, /* (after IN data) */
MUSB_EP0_STAGE_ACKWAIT, /* after zlp, before statusin */
} __attribute__ ((packed));
/* OTG protocol constants */
......@@ -221,18 +221,18 @@ enum musb_g_ep0_state {
#if defined(CONFIG_USB_TUSB6010)
#define musb_ep_select(_mbase, _epnum) \
musb_writeb((_mbase), MUSB_INDEX, (_epnum))
#define MGC_END_OFFSET MUSB_TUSB_OFFSET
#define MUSB_EP_OFFSET MUSB_TUSB_OFFSET
/* "flat" mapping: each endpoint has its own i/o address */
#elif defined(MUSB_FLAT_REG)
#define musb_ep_select(_mbase, _epnum) (((void)(_mbase)),((void)(_epnum)))
#define MGC_END_OFFSET MUSB_FLAT_OFFSET
#define MUSB_EP_OFFSET MUSB_FLAT_OFFSET
/* "indexed" mapping: INDEX register controls register bank select */
#else
#define musb_ep_select(_mbase, _epnum) \
musb_writeb((_mbase), MUSB_INDEX, (_epnum))
#define MGC_END_OFFSET MUSB_INDEXED_OFFSET
#define MUSB_EP_OFFSET MUSB_INDEXED_OFFSET
#endif
/****************************** FUNCTIONS ********************************/
......@@ -450,11 +450,6 @@ struct musb {
struct usb_gadget_driver *gadget_driver; /* its driver */
#endif
#ifdef CONFIG_USB_MUSB_OTG
/* FIXME this can't be OTG-specific ... ? */
u8 delay_port_power_off;
#endif
#ifdef MUSB_CONFIG_PROC_FS
struct proc_dir_entry *proc_entry;
#endif
......
drivers/usb/musb/musbhsdma.c
View file @ 857355a7
......@@ -44,14 +44,14 @@
#include "omap2430.h"
#endif
#define MGC_O_HSDMA_BASE 0x200
#define MGC_O_HSDMA_INTR (MGC_O_HSDMA_BASE + 0)
#define MGC_O_HSDMA_CONTROL 0x4
#define MGC_O_HSDMA_ADDRESS 0x8
#define MGC_O_HSDMA_COUNT 0xc
#define MUSB_HSDMA_BASE 0x200
#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
#define MUSB_HSDMA_CONTROL 0x4
#define MUSB_HSDMA_ADDRESS 0x8
#define MUSB_HSDMA_COUNT 0xc
#define MGC_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \
(MGC_O_HSDMA_BASE + (_bChannel << 4) + _offset)
#define MUSB_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \
(MUSB_HSDMA_BASE + (_bChannel << 4) + _offset)
/* control register (16-bit): */
#define MUSB_HSDMA_ENABLE_SHIFT 0
......@@ -62,12 +62,12 @@
#define MUSB_HSDMA_BUSERROR_SHIFT 8
#define MUSB_HSDMA_BURSTMODE_SHIFT 9
#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
#define MGC_HSDMA_BURSTMODE_UNSPEC 0
#define MGC_HSDMA_BURSTMODE_INCR4 1
#define MGC_HSDMA_BURSTMODE_INCR8 2
#define MGC_HSDMA_BURSTMODE_INCR16 3
#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
#define MUSB_HSDMA_BURSTMODE_INCR4 1
#define MUSB_HSDMA_BURSTMODE_INCR8 2
#define MUSB_HSDMA_BURSTMODE_INCR16 3
#define MGC_HSDMA_CHANNELS 8
#define MUSB_HSDMA_CHANNELS 8
struct musb_dma_controller;
......@@ -84,7 +84,7 @@ struct musb_dma_channel {
struct musb_dma_controller {
struct dma_controller Controller;
struct musb_dma_channel aChannel[MGC_HSDMA_CHANNELS];
struct musb_dma_channel aChannel[MUSB_HSDMA_CHANNELS];
void *pDmaPrivate;
void __iomem *pCoreBase;
u8 bChannelCount;
......@@ -112,7 +112,7 @@ static int dma_controller_stop(struct dma_controller *c)
dev_err(musb->controller,
"Stopping DMA controller while channel active\n");
for (bBit = 0; bBit < MGC_HSDMA_CHANNELS; bBit++) {
for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
if (controller->bmUsedChannels & (1 << bBit)) {
pChannel = &(controller->aChannel[bBit].Channel);
dma_channel_release(pChannel);
......@@ -134,7 +134,7 @@ static struct dma_channel* dma_channel_allocate(struct dma_controller *c,
struct musb_dma_controller *controller =
container_of(c, struct musb_dma_controller, Controller);
for (bBit = 0; bBit < MGC_HSDMA_CHANNELS; bBit++) {
for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
if (!(controller->bmUsedChannels & (1 << bBit))) {
controller->bmUsedChannels |= (1 << bBit);
pImplChannel = &(controller->aChannel[bBit]);
......@@ -191,13 +191,13 @@ static void configure_channel(struct dma_channel *pChannel,
}
if (packet_sz >= 64) {
csr |=
MGC_HSDMA_BURSTMODE_INCR16 << MUSB_HSDMA_BURSTMODE_SHIFT;
MUSB_HSDMA_BURSTMODE_INCR16 << MUSB_HSDMA_BURSTMODE_SHIFT;
} else if (packet_sz >= 32) {
csr |=
MGC_HSDMA_BURSTMODE_INCR8 << MUSB_HSDMA_BURSTMODE_SHIFT;
MUSB_HSDMA_BURSTMODE_INCR8 << MUSB_HSDMA_BURSTMODE_SHIFT;
} else if (packet_sz >= 16) {
csr |=
MGC_HSDMA_BURSTMODE_INCR4 << MUSB_HSDMA_BURSTMODE_SHIFT;
MUSB_HSDMA_BURSTMODE_INCR4 << MUSB_HSDMA_BURSTMODE_SHIFT;
}
}
......@@ -208,15 +208,15 @@ static void configure_channel(struct dma_channel *pChannel,
/* address/count */
musb_writel(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_ADDRESS),
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS),
dma_addr);
musb_writel(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_COUNT),
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT),
len);
/* control (this should start things) */
musb_writew(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_CONTROL),
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL),
csr);
}
......@@ -263,31 +263,31 @@ static int dma_channel_abort(struct dma_channel *pChannel)
if (pImplChannel->transmit) {
csr = musb_readw(mbase,
MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR));
MUSB_EP_OFFSET(pImplChannel->epnum,MUSB_TXCSR));
csr &= ~(MUSB_TXCSR_AUTOSET |
MUSB_TXCSR_DMAENAB |
MUSB_TXCSR_DMAMODE);
musb_writew(mbase,
MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
MUSB_EP_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
csr);
}
else {
csr = musb_readw(mbase,
MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR));
MUSB_EP_OFFSET(pImplChannel->epnum,MUSB_RXCSR));
csr &= ~(MUSB_RXCSR_AUTOCLEAR |
MUSB_RXCSR_DMAENAB |
MUSB_RXCSR_DMAMODE);
musb_writew(mbase,
MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR),
MUSB_EP_OFFSET(pImplChannel->epnum,MUSB_RXCSR),
csr);
}
musb_writew(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_CONTROL), 0);
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL), 0);
musb_writel(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_ADDRESS), 0);
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS), 0);
musb_writel(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel, MGC_O_HSDMA_COUNT), 0);
MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT), 0);
pChannel->status = MUSB_DMA_STATUS_FREE;
}
......@@ -307,28 +307,28 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
u8 int_hsdma;
irqreturn_t retval = IRQ_NONE;
int_hsdma = musb_readb(mbase, MGC_O_HSDMA_INTR);
int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
if (!int_hsdma)
goto done;
for (bChannel = 0; bChannel < MGC_HSDMA_CHANNELS; bChannel++) {
for (bChannel = 0; bChannel < MUSB_HSDMA_CHANNELS; bChannel++) {
if (int_hsdma & (1 << bChannel)) {
pImplChannel = (struct musb_dma_channel *)
&(controller->aChannel[bChannel]);
pChannel = &pImplChannel->Channel;
csr = musb_readw(mbase,
MGC_HSDMA_CHANNEL_OFFSET(bChannel,
MGC_O_HSDMA_CONTROL));
MUSB_HSDMA_CHANNEL_OFFSET(bChannel,
MUSB_HSDMA_CONTROL));
if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
pImplChannel->Channel.status =
MUSB_DMA_STATUS_BUS_ABORT;
} else {
dwAddress = musb_readl(mbase,
MGC_HSDMA_CHANNEL_OFFSET(
MUSB_HSDMA_CHANNEL_OFFSET(
bChannel,
MGC_O_HSDMA_ADDRESS));
MUSB_HSDMA_ADDRESS));
pChannel->actual_len =
dwAddress - pImplChannel->dwStartAddress;
......@@ -356,7 +356,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
musb_ep_select(mbase,
pImplChannel->epnum);
musb_writew(mbase,
MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
MUSB_EP_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
MUSB_TXCSR_TXPKTRDY);
} else
musb_dma_completion(
......@@ -403,7 +403,7 @@ dma_controller_create(struct musb *musb, void __iomem *pCoreBase)
GFP_KERNEL)))
return NULL;
controller->bChannelCount = MGC_HSDMA_CHANNELS;
controller->bChannelCount = MUSB_HSDMA_CHANNELS;
controller->pDmaPrivate = musb;
controller->pCoreBase = pCoreBase;
......
drivers/usb/musb/plat_uds.c
View file @ 857355a7
......@@ -467,7 +467,7 @@ static irqreturn_t musb_stage0_irq(struct musb * musb, u8 int_usb,
* a_wait_vrise_tmout triggers VBUS_ERROR transitions
*/
musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
musb->ep0_stage = MGC_END0_START;
musb->ep0_stage = MUSB_EP0_START;
musb->xceiv.state = OTG_STATE_A_IDLE;
MUSB_HST_MODE(musb);
musb_set_vbus(musb, 1);
......@@ -550,14 +550,13 @@ static irqreturn_t musb_stage0_irq(struct musb * musb, u8 int_usb,
musb->is_active = 1;
set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
musb->ep0_stage = MGC_END0_START;
musb->ep0_stage = MUSB_EP0_START;
#ifdef CONFIG_USB_MUSB_OTG
/* flush endpoints when transitioning from Device Mode */
if (is_peripheral_active(musb)) {
// REVISIT HNP; just force disconnect
}
musb->delay_port_power_off = FALSE;
musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
......@@ -604,6 +603,7 @@ static irqreturn_t musb_stage0_irq(struct musb * musb, u8 int_usb,
* only host sees babble; only peripheral sees bus reset.
*/
if (int_usb & MUSB_INTR_RESET) {
#ifdef CONFIG_USB_MUSB_HDRC_HCD
if (devctl & MUSB_DEVCTL_HM) {
/*
* Looks like non-HS BABBLE can be ignored, but
......@@ -618,7 +618,9 @@ static irqreturn_t musb_stage0_irq(struct musb * musb, u8 int_usb,
ERR("Stopping host session because of babble\n");
musb_writeb(mbase, MUSB_DEVCTL, 0);
}
} else {
} else
#endif /* CONFIG_USB_MUSB_HDRC_HCD */
{
DBG(1, "BUS RESET\n");
musb_g_reset(musb);
......@@ -1380,7 +1382,7 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
#endif
hw_ep->regs = MGC_END_OFFSET(i, 0) + mbase;
hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
#ifdef CONFIG_USB_MUSB_HDRC_HCD
hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
hw_ep->rx_reinit = 1;
......@@ -1710,7 +1712,6 @@ musb_srp_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t n)
{
struct musb *musb=dev_to_musb(dev);
unsigned long flags;
unsigned short srp;
if (sscanf(buf, "%hu", &srp) != 1
......@@ -1719,10 +1720,8 @@ musb_srp_store(struct device *dev, struct device_attribute *attr,
return -EINVAL;
}
spin_lock_irqsave(&musb->lock, flags);
if (srp == 1)
musb_g_wakeup(musb);
spin_unlock_irqrestore(&musb->lock, flags);
return n;
}
......
drivers/usb/musb/virthub.c
View file @ 857355a7
......@@ -85,11 +85,14 @@ static void musb_port_suspend(struct musb *musb, u8 bSuspend)
&& musb->xceiv.host->b_hnp_enable;
musb_platform_try_idle(musb, 0);
break;
#ifdef CONFIG_USB_MUSB_OTG
case OTG_STATE_B_HOST:
musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
MUSB_DEV_MODE(musb);
/* REVISIT restore setting of MUSB_DEVCTL_HR */
musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
musb->is_active = is_otg_enabled(musb)
&& musb->xceiv.host->b_hnp_enable;
musb_platform_try_idle(musb, 0);
break;
#endif
default:
DBG(1, "bogus rh suspend? %s\n",
otg_state_string(musb));
......@@ -113,10 +116,9 @@ static void musb_port_reset(struct musb *musb, u8 bReset)
void __iomem *mbase = musb->mregs;
#ifdef CONFIG_USB_MUSB_OTG
/* REVISIT this looks wrong for HNP */
u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
if (musb->delay_port_power_off || !(devctl & MUSB_DEVCTL_HM)) {
if (musb->xceiv.state == OTG_STATE_B_IDLE) {
DBG(2, "HNP: Returning from HNP, not resetting hub as b_idle\n");
musb->port1_status &= ~USB_PORT_STAT_RESET;
return;
}
#endif
......
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