Commit 847b9dfc authored by Chris Dearman's avatar Chris Dearman Committed by Ralf Baechle

[MIPS] MT: Initialise all writable bits in Cause register to zero.

Recent 34Ks come out of reset with WP enabled on VPE 1 so we take an
immediate exception when starting the second VPE.
Signed-off-by: default avatarChris Dearman <chris@mips.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent bca70d24
...@@ -203,7 +203,7 @@ void plat_smp_setup(void) ...@@ -203,7 +203,7 @@ void plat_smp_setup(void)
write_vpe_c0_config( read_c0_config()); write_vpe_c0_config( read_c0_config());
/* make sure there are no software interrupts pending */ /* make sure there are no software interrupts pending */
write_vpe_c0_cause(read_vpe_c0_cause() & ~(C_SW1|C_SW0)); write_vpe_c0_cause(0);
/* Propagate Config7 */ /* Propagate Config7 */
write_vpe_c0_config7(read_c0_config7()); write_vpe_c0_config7(read_c0_config7());
......
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