Commit 82c07cbb authored by Thomas Gleixner's avatar Thomas Gleixner

x86: Disable SPARSE_IRQ, DMAR, INTR_REMAP when PREEMPT_RT=y

Memory allocations in irq/preempt disabled regions is the main cause
of grief with these features. Needs some real work to get that solved.
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 0dfea57f
...@@ -281,6 +281,7 @@ config X86_X2APIC ...@@ -281,6 +281,7 @@ config X86_X2APIC
config SPARSE_IRQ config SPARSE_IRQ
bool "Support sparse irq numbering" bool "Support sparse irq numbering"
depends on PCI_MSI || HT_IRQ depends on PCI_MSI || HT_IRQ
depends on !PREEMPT_RT
---help--- ---help---
This enables support for sparse irqs. This is useful for distro This enables support for sparse irqs. This is useful for distro
kernels that want to define a high CONFIG_NR_CPUS value but still kernels that want to define a high CONFIG_NR_CPUS value but still
...@@ -1902,7 +1903,7 @@ config PCI_MMCONFIG ...@@ -1902,7 +1903,7 @@ config PCI_MMCONFIG
config DMAR config DMAR
bool "Support for DMA Remapping Devices (EXPERIMENTAL)" bool "Support for DMA Remapping Devices (EXPERIMENTAL)"
depends on PCI_MSI && ACPI && EXPERIMENTAL depends on PCI_MSI && ACPI && EXPERIMENTAL && !PREEMPT_RT
help help
DMA remapping (DMAR) devices support enables independent address DMA remapping (DMAR) devices support enables independent address
translations for Direct Memory Access (DMA) from devices. translations for Direct Memory Access (DMA) from devices.
...@@ -1945,6 +1946,7 @@ config DMAR_FLOPPY_WA ...@@ -1945,6 +1946,7 @@ config DMAR_FLOPPY_WA
config INTR_REMAP config INTR_REMAP
bool "Support for Interrupt Remapping (EXPERIMENTAL)" bool "Support for Interrupt Remapping (EXPERIMENTAL)"
depends on X86_64 && X86_IO_APIC && PCI_MSI && ACPI && EXPERIMENTAL depends on X86_64 && X86_IO_APIC && PCI_MSI && ACPI && EXPERIMENTAL
depends on !PREEMPT_RT
---help--- ---help---
Supports Interrupt remapping for IO-APIC and MSI devices. Supports Interrupt remapping for IO-APIC and MSI devices.
To use x2apic mode in the CPU's which support x2APIC enhancements or To use x2apic mode in the CPU's which support x2APIC enhancements or
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