Enable partial low interrupt latency mode for ARM1136

This patch is a workaround for the 364296 ARM1136 r0pX errata
(possible cache data corruption with hit-under-miss enabled). It sets
the undocumented bit 31 in the auxiliary control register and the FI bit in
the control register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

arch/arm/mm/proc-v6.S

@@ -237,11 +237,25 @@ __v6_setup:
 	orr	r0, r0, #(0xf << 20)
 	mcr	p15, 0, r0, c1, c0, 2		@ Enable full access to VFP
 #endif
+	/* Workaround for the 364296 ARM1136 r0pX errata (possible cache data
+	 * corruption with hit-under-miss enabled). The conditional code below
+	 * (setting the undocumented bit 31 in the auxiliary control register
+	 * and the FI bit in the control register) disables hit-under-miss
+	 * without putting the processor into full low interrupt latency mode.
+	 */
+	ldr	r5, =0x4107b360			@ id for ARM1136 r0pX
+	mrc	p15, 0, r0, c0, c0, 0		@ get processor id
+	bic	r0, r0, #0xf			@ mask out part bits [3:0]
+	teq	r0, r5				@ check for the faulty core
+	mrceq	p15, 0, r0, c1, c0, 1		@ load aux control reg
+	orreq	r0, r0, #0x80000000		@ set bit 31
+	mcreq	p15, 0, r0, c1, c0, 1		@ write aux control reg
 	mrc	p15, 0, r0, c1, c0, 0		@ read control register
 	ldr	r5, v6_cr1_clear		@ get mask for bits to clear
 	bic	r0, r0, r5			@ clear bits them
 	ldr	r5, v6_cr1_set			@ get mask for bits to set
 	orr	r0, r0, r5			@ set them
+	orreq	r0, r0, #0x00200000		@ set the FI bit
 	mov	pc, lr				@ return to head.S:__ret
 
 	/*