Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
L
linux-davinci
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Redmine
Redmine
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Operations
Operations
Metrics
Environments
Analytics
Analytics
CI / CD
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
linux
linux-davinci
Commits
7e3bfc7c
Commit
7e3bfc7c
authored
Apr 05, 2006
by
Ralf Baechle
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
[MIPS] Handle IDE PIO cache aliases on SMP.
Signed-off-by:
Ralf Baechle
<
ralf@linux-mips.org
>
parent
bb12d612
Changes
7
Hide whitespace changes
Inline
Side-by-side
Showing
7 changed files
with
60 additions
and
2 deletions
+60
-2
arch/mips/mm/c-r3k.c
arch/mips/mm/c-r3k.c
+5
-0
arch/mips/mm/c-r4k.c
arch/mips/mm/c-r4k.c
+1
-0
arch/mips/mm/c-sb1.c
arch/mips/mm/c-sb1.c
+1
-0
arch/mips/mm/c-tx39.c
arch/mips/mm/c-tx39.c
+7
-0
arch/mips/mm/cache.c
arch/mips/mm/cache.c
+1
-0
include/asm-mips/cacheflush.h
include/asm-mips/cacheflush.h
+1
-0
include/asm-mips/mach-generic/ide.h
include/asm-mips/mach-generic/ide.h
+44
-2
No files found.
arch/mips/mm/c-r3k.c
View file @
7e3bfc7c
...
...
@@ -260,6 +260,10 @@ static void r3k_flush_cache_page(struct vm_area_struct *vma, unsigned long page,
{
}
static
void
local_r3k_flush_data_cache_page
(
unsigned
long
addr
)
{
}
static
void
r3k_flush_data_cache_page
(
unsigned
long
addr
)
{
}
...
...
@@ -335,6 +339,7 @@ void __init r3k_cache_init(void)
flush_icache_range
=
r3k_flush_icache_range
;
flush_cache_sigtramp
=
r3k_flush_cache_sigtramp
;
local_flush_data_cache_page
=
local_r3k_flush_data_cache_page
;
flush_data_cache_page
=
r3k_flush_data_cache_page
;
_dma_cache_wback_inv
=
r3k_dma_cache_wback_inv
;
...
...
arch/mips/mm/c-r4k.c
View file @
7e3bfc7c
...
...
@@ -1199,6 +1199,7 @@ void __init r4k_cache_init(void)
flush_cache_sigtramp
=
r4k_flush_cache_sigtramp
;
flush_icache_all
=
r4k_flush_icache_all
;
local_flush_data_cache_page
=
local_r4k_flush_data_cache_page
;
flush_data_cache_page
=
r4k_flush_data_cache_page
;
flush_icache_range
=
r4k_flush_icache_range
;
...
...
arch/mips/mm/c-sb1.c
View file @
7e3bfc7c
...
...
@@ -528,6 +528,7 @@ void sb1_cache_init(void)
flush_cache_page
=
sb1_flush_cache_page
;
flush_cache_sigtramp
=
sb1_flush_cache_sigtramp
;
local_flush_data_cache_page
=
(
void
*
)
sb1_nop
;
flush_data_cache_page
=
(
void
*
)
sb1_nop
;
/* Full flush */
...
...
arch/mips/mm/c-tx39.c
View file @
7e3bfc7c
...
...
@@ -216,6 +216,11 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
tx39_blast_icache_page_indexed
(
page
);
}
static
void
local_tx39_flush_data_cache_page
(
void
*
addr
)
{
tx39_blast_dcache_page
(
addr
);
}
static
void
tx39_flush_data_cache_page
(
unsigned
long
addr
)
{
tx39_blast_dcache_page
(
addr
);
...
...
@@ -381,6 +386,7 @@ void __init tx39_cache_init(void)
flush_icache_range
=
(
void
*
)
tx39h_flush_icache_all
;
flush_cache_sigtramp
=
(
void
*
)
tx39h_flush_icache_all
;
local_flush_data_cache_page
=
(
void
*
)
tx39h_flush_icache_all
;
flush_data_cache_page
=
(
void
*
)
tx39h_flush_icache_all
;
_dma_cache_wback_inv
=
tx39h_dma_cache_wback_inv
;
...
...
@@ -406,6 +412,7 @@ void __init tx39_cache_init(void)
flush_icache_range
=
tx39_flush_icache_range
;
flush_cache_sigtramp
=
tx39_flush_cache_sigtramp
;
local_flush_data_cache_page
=
local_tx39_flush_data_cache_page
;
flush_data_cache_page
=
tx39_flush_data_cache_page
;
_dma_cache_wback_inv
=
tx39_dma_cache_wback_inv
;
...
...
arch/mips/mm/cache.c
View file @
7e3bfc7c
...
...
@@ -30,6 +30,7 @@ void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page);
/* MIPS specific cache operations */
void
(
*
flush_cache_sigtramp
)(
unsigned
long
addr
);
void
(
*
local_flush_data_cache_page
)(
void
*
addr
);
void
(
*
flush_data_cache_page
)(
unsigned
long
addr
);
void
(
*
flush_icache_all
)(
void
);
...
...
include/asm-mips/cacheflush.h
View file @
7e3bfc7c
...
...
@@ -74,6 +74,7 @@ static inline void copy_from_user_page(struct vm_area_struct *vma,
extern
void
(
*
flush_cache_sigtramp
)(
unsigned
long
addr
);
extern
void
(
*
flush_icache_all
)(
void
);
extern
void
(
*
local_flush_data_cache_page
)(
void
*
addr
);
extern
void
(
*
flush_data_cache_page
)(
unsigned
long
addr
);
/*
...
...
include/asm-mips/mach-generic/ide.h
View file @
7e3bfc7c
...
...
@@ -104,65 +104,107 @@ static __inline__ unsigned long ide_default_io_base(int index)
#endif
/* MIPS port and memory-mapped I/O string operations. */
static
inline
void
__ide_flush_prologue
(
void
)
{
#ifdef CONFIG_SMP
if
(
cpu_has_dc_aliases
)
preempt_disable
();
#endif
}
static
inline
void
__ide_flush_epilogue
(
void
)
{
#ifdef CONFIG_SMP
if
(
cpu_has_dc_aliases
)
preempt_enable
();
#endif
}
static
inline
void
__ide_flush_dcache_range
(
unsigned
long
addr
,
unsigned
long
size
)
{
if
(
cpu_has_dc_aliases
)
{
unsigned
long
end
=
addr
+
size
;
for
(;
addr
<
end
;
addr
+=
PAGE_SIZE
)
flush_dcache_page
(
virt_to_page
(
addr
));
while
(
addr
<
end
)
{
local_flush_data_cache_page
((
void
*
)
addr
);
addr
+=
PAGE_SIZE
;
}
}
}
/*
* insw() and gang might be called with interrupts disabled, so we can't
* send IPIs for flushing due to the potencial of deadlocks, see the comment
* above smp_call_function() in arch/mips/kernel/smp.c. We work around the
* problem by disabling preemption so we know we actually perform the flush
* on the processor that actually has the lines to be flushed which hopefully
* is even better for performance anyway.
*/
static
inline
void
__ide_insw
(
unsigned
long
port
,
void
*
addr
,
unsigned
int
count
)
{
__ide_flush_prologue
();
insw
(
port
,
addr
,
count
);
__ide_flush_dcache_range
((
unsigned
long
)
addr
,
count
*
2
);
__ide_flush_epilogue
();
}
static
inline
void
__ide_insl
(
unsigned
long
port
,
void
*
addr
,
unsigned
int
count
)
{
__ide_flush_prologue
();
insl
(
port
,
addr
,
count
);
__ide_flush_dcache_range
((
unsigned
long
)
addr
,
count
*
4
);
__ide_flush_epilogue
();
}
static
inline
void
__ide_outsw
(
unsigned
long
port
,
const
void
*
addr
,
unsigned
long
count
)
{
__ide_flush_prologue
();
outsw
(
port
,
addr
,
count
);
__ide_flush_dcache_range
((
unsigned
long
)
addr
,
count
*
2
);
__ide_flush_epilogue
();
}
static
inline
void
__ide_outsl
(
unsigned
long
port
,
const
void
*
addr
,
unsigned
long
count
)
{
__ide_flush_prologue
();
outsl
(
port
,
addr
,
count
);
__ide_flush_dcache_range
((
unsigned
long
)
addr
,
count
*
4
);
__ide_flush_epilogue
();
}
static
inline
void
__ide_mm_insw
(
void
__iomem
*
port
,
void
*
addr
,
u32
count
)
{
__ide_flush_prologue
();
readsw
(
port
,
addr
,
count
);
__ide_flush_dcache_range
((
unsigned
long
)
addr
,
count
*
2
);
__ide_flush_epilogue
();
}
static
inline
void
__ide_mm_insl
(
void
__iomem
*
port
,
void
*
addr
,
u32
count
)
{
__ide_flush_prologue
();
readsl
(
port
,
addr
,
count
);
__ide_flush_dcache_range
((
unsigned
long
)
addr
,
count
*
4
);
__ide_flush_epilogue
();
}
static
inline
void
__ide_mm_outsw
(
void
__iomem
*
port
,
void
*
addr
,
u32
count
)
{
__ide_flush_prologue
();
writesw
(
port
,
addr
,
count
);
__ide_flush_dcache_range
((
unsigned
long
)
addr
,
count
*
2
);
__ide_flush_epilogue
();
}
static
inline
void
__ide_mm_outsl
(
void
__iomem
*
port
,
void
*
addr
,
u32
count
)
{
__ide_flush_prologue
();
writesl
(
port
,
addr
,
count
);
__ide_flush_dcache_range
((
unsigned
long
)
addr
,
count
*
4
);
__ide_flush_epilogue
();
}
/* ide_insw calls insw, not __ide_insw. Why? */
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment