Commit 7a69c701 authored by Shaohua Li's avatar Shaohua Li Committed by Greg Kroah-Hartman

PCI: disable ASPM on pre-1.1 PCIe devices

commit 149e1637 upstream

Disable ASPM on pre-1.1 PCIe devices, as many of them don't implement it
correctly.
Tested-by: default avatarJack Howarth <howarth@bromo.msbb.uc.edu>
Signed-off-by: default avatarShaohua Li <shaohua.li@intel.com>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Cc: Chuck Ebbert <cebbert@redhat.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 7a17866e
...@@ -510,6 +510,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev) ...@@ -510,6 +510,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
{ {
struct pci_dev *child_dev; struct pci_dev *child_dev;
int child_pos; int child_pos;
u32 reg32;
/* /*
* Some functions in a slot might not all be PCIE functions, very * Some functions in a slot might not all be PCIE functions, very
...@@ -519,6 +520,18 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev) ...@@ -519,6 +520,18 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
if (!child_pos) if (!child_pos)
return -EINVAL; return -EINVAL;
/*
* Disable ASPM for pre-1.1 PCIe device, we follow MS to use
* RBER bit to determine if a function is 1.1 version device
*/
pci_read_config_dword(child_dev, child_pos + PCI_EXP_DEVCAP,
&reg32);
if (!(reg32 & PCI_EXP_DEVCAP_RBER)) {
printk("Pre-1.1 PCIe device detected, "
"disable ASPM for %s\n", pci_name(pdev));
return -EINVAL;
}
} }
return 0; return 0;
} }
......
...@@ -1047,7 +1047,8 @@ int pci_scan_slot(struct pci_bus *bus, int devfn) ...@@ -1047,7 +1047,8 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
} }
} }
if (bus->self) /* only one slot has pcie device */
if (bus->self && nr)
pcie_aspm_init_link_state(bus->self); pcie_aspm_init_link_state(bus->self);
return nr; return nr;
......
...@@ -373,6 +373,7 @@ ...@@ -373,6 +373,7 @@
#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */ #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */ #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
#define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
#define PCI_EXP_DEVCTL 8 /* Device Control */ #define PCI_EXP_DEVCTL 8 /* Device Control */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment