Commit 70e46f48 authored by Ralf Baechle's avatar Ralf Baechle

[MIPS] VSMP: Synchronize cp0 counters on bootup.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent e79f55a8
......@@ -153,6 +153,8 @@ static void __init smp_copy_vpe_config(void)
/* Propagate Config7 */
write_vpe_c0_config7(read_c0_config7());
write_vpe_c0_count(read_c0_count());
}
static unsigned int __init smp_vpe_init(unsigned int tc, unsigned int mvpconf0,
......
......@@ -209,6 +209,7 @@ static unsigned int __init estimate_cpu_frequency(void)
#endif
#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
unsigned long flags;
unsigned int start;
local_irq_save(flags);
......@@ -217,13 +218,13 @@ static unsigned int __init estimate_cpu_frequency(void)
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
/* Start r4k counter. */
write_c0_count(0);
start = read_c0_count();
/* Read counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
count = read_c0_count();
count = read_c0_count() - start;
/* restore interrupts */
local_irq_restore(flags);
......
......@@ -352,6 +352,8 @@ do { \
#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
#define read_vpe_c0_vpeconf0() mftc0(1, 2)
#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
#define read_vpe_c0_count() mftc0(9, 0)
#define write_vpe_c0_count(val) mttc0(9, 0, val)
#define read_vpe_c0_status() mftc0(12, 0)
#define write_vpe_c0_status(val) mttc0(12, 0, val)
#define read_vpe_c0_cause() mftc0(13, 0)
......
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