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linux
linux-davinci
Commits
70e46f48
Commit
70e46f48
authored
Oct 31, 2006
by
Ralf Baechle
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[MIPS] VSMP: Synchronize cp0 counters on bootup.
Signed-off-by:
Ralf Baechle
<
ralf@linux-mips.org
>
parent
e79f55a8
Changes
3
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3 changed files
with
7 additions
and
2 deletions
+7
-2
arch/mips/kernel/smp-mt.c
arch/mips/kernel/smp-mt.c
+2
-0
arch/mips/mips-boards/generic/time.c
arch/mips/mips-boards/generic/time.c
+3
-2
include/asm-mips/mipsmtregs.h
include/asm-mips/mipsmtregs.h
+2
-0
No files found.
arch/mips/kernel/smp-mt.c
View file @
70e46f48
...
...
@@ -153,6 +153,8 @@ static void __init smp_copy_vpe_config(void)
/* Propagate Config7 */
write_vpe_c0_config7
(
read_c0_config7
());
write_vpe_c0_count
(
read_c0_count
());
}
static
unsigned
int
__init
smp_vpe_init
(
unsigned
int
tc
,
unsigned
int
mvpconf0
,
...
...
arch/mips/mips-boards/generic/time.c
View file @
70e46f48
...
...
@@ -209,6 +209,7 @@ static unsigned int __init estimate_cpu_frequency(void)
#endif
#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
unsigned
long
flags
;
unsigned
int
start
;
local_irq_save
(
flags
);
...
...
@@ -217,13 +218,13 @@ static unsigned int __init estimate_cpu_frequency(void)
while
(
!
(
CMOS_READ
(
RTC_REG_A
)
&
RTC_UIP
));
/* Start r4k counter. */
write_c0_count
(
0
);
start
=
read_c0_count
(
);
/* Read counter exactly on falling edge of update flag */
while
(
CMOS_READ
(
RTC_REG_A
)
&
RTC_UIP
);
while
(
!
(
CMOS_READ
(
RTC_REG_A
)
&
RTC_UIP
));
count
=
read_c0_count
();
count
=
read_c0_count
()
-
start
;
/* restore interrupts */
local_irq_restore
(
flags
);
...
...
include/asm-mips/mipsmtregs.h
View file @
70e46f48
...
...
@@ -352,6 +352,8 @@ do { \
#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
#define read_vpe_c0_vpeconf0() mftc0(1, 2)
#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
#define read_vpe_c0_count() mftc0(9, 0)
#define write_vpe_c0_count(val) mttc0(9, 0, val)
#define read_vpe_c0_status() mftc0(12, 0)
#define write_vpe_c0_status(val) mttc0(12, 0, val)
#define read_vpe_c0_cause() mftc0(13, 0)
...
...
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