Commit 6fc6d9c1 authored by Tony Lindgren's avatar Tony Lindgren

ARM: OMAP: Fix SRAM compile for omap1

Recent SRAM rearranging broke omap1 compile, this fixes it.

After 2.6.25 we should move plat-omap/sram-fn.S to
mach-omap1/sram.S.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent c40ad8de
......@@ -18,7 +18,7 @@
/*
* Reprograms ULPD and CKCTL.
*/
ENTRY(sram_reprogram_clock)
ENTRY(omap1_sram_reprogram_clock)
stmfd sp!, {r0 - r12, lr} @ save registers on stack
mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000
......@@ -53,5 +53,5 @@ lock: ldrh r4, [r2], #0 @ read back dpll value
out:
ldmfd sp!, {r0 - r12, pc} @ restore regs and return
ENTRY(sram_reprogram_clock_sz)
.word . - sram_reprogram_clock
ENTRY(omap1_sram_reprogram_clock_sz)
.word . - omap1_sram_reprogram_clock
......@@ -338,8 +338,9 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
int __init omap1_sram_init(void)
{
_omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock,
sram_reprogram_clock_sz);
_omap_sram_reprogram_clock =
omap_sram_push(omap1_sram_reprogram_clock,
omap1_sram_reprogram_clock_sz);
return 0;
}
......
......@@ -24,6 +24,9 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
/* Do not use these */
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
extern unsigned long omap1_sram_reprogram_clock_sz;
extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
extern unsigned long omap24xx_sram_reprogram_clock_sz;
......
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