Commit 6a05888d authored by Ralf Baechle's avatar Ralf Baechle

[MIPS] SMTC: The MT ASE requires to initialize c0_pagemask and c0_wired.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8e8a52ed
...@@ -1384,6 +1384,13 @@ void __init per_cpu_trap_init(void) ...@@ -1384,6 +1384,13 @@ void __init per_cpu_trap_init(void)
cpu_cache_init(); cpu_cache_init();
tlb_init(); tlb_init();
#ifdef CONFIG_MIPS_MT_SMTC #ifdef CONFIG_MIPS_MT_SMTC
} else if (!secondaryTC) {
/*
* First TC in non-boot VPE must do subset of tlb_init()
* for MMU countrol registers.
*/
write_c0_pagemask(PM_DEFAULT_MASK);
write_c0_wired(0);
} }
#endif /* CONFIG_MIPS_MT_SMTC */ #endif /* CONFIG_MIPS_MT_SMTC */
} }
......
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