Add support for the RealView/EB MPCore revC platform

The kernel originally supported revB only. This patch enables revC by
default and adds a config option for building the kernel for the revB
platform.
Signed-off-by: Harry Fearnhamm <Harry.Fearnhamm@arm.com>

arch/arm/mach-realview/Kconfig

@@ -16,4 +16,14 @@ config REALVIEW_MPCORE
 	  kernel built with this option enabled is not compatible with
 	  other tiles.
 
+config REALVIEW_MPCORE_REVB
+	bool "Support MPcore RevB tile"
+	depends on REALVIEW_MPCORE
+	default n
+	help
+	  Enable support for the MPCore RevB tile on the Realview platform.
+	  Since there are device address differences, a
+	  kernel built with this option enabled is not compatible with
+	  other tiles.
+
 endmenu

arch/arm/mach-realview/realview_eb.c

@@ -139,9 +139,9 @@ static void __init gic_init_irq(void)
 #ifdef CONFIG_REALVIEW_MPCORE
 	unsigned int pldctrl;
 	writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
-	pldctrl = readl(__io_address(REALVIEW_SYS_BASE)	+ 0xd8);
+	pldctrl = readl(__io_address(REALVIEW_SYS_BASE)	+ REALVIEW_MPCORE_SYS_PLD_CTRL1);
 	pldctrl |= 0x00800000;	/* New irq mode */
-	writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + 0xd8);
+	writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1);
 	writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
 #endif
 	gic_dist_init(__io_address(REALVIEW_GIC_DIST_BASE));

arch/arm/mm/proc-v6.S

@@ -208,8 +208,12 @@ __v6_setup:
 	/* Set up the SCU on core 0 only */
 	mrc	p15, 0, r0, c0, c0, 5		@ CPU core number
 	ands	r0, r0, #15
+#ifdef CONFIG_REALVIEW_MPCORE_REVB
 	moveq	r0, #0x10000000 @ SCU_BASE
 	orreq	r0, r0, #0x00100000
+#else
+	moveq	r0, #0x1F000000			@ SCU control registers
+#endif
 	ldreq	r5, [r0, #SCU_CTRL]
 	orreq	r5, r5, #1
 	streq	r5, [r0, #SCU_CTRL]

include/asm-arm/arch-realview/hardware.h

@@ -26,7 +26,7 @@
 #include <asm/arch/platform.h>
 
 /* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x)		(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
+#define IO_ADDRESS(x)		((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
 #define __io_address(n)		__io(IO_ADDRESS(n))
 
 #endif

include/asm-arm/arch-realview/platform.h

@@ -207,11 +207,20 @@
 #define REALVIEW_GIC_CPU_BASE         0x10040000	/* Generic interrupt controller CPU interface */
 #define REALVIEW_GIC_DIST_BASE        0x10041000	/* Generic interrupt controller distributor */
 #else
-#define REALVIEW_MPCORE_SCU_BASE	0x10100000	/*  SCU registers */
-#define REALVIEW_GIC_CPU_BASE		0x10100100	/* Generic interrupt controller CPU interface */
-#define REALVIEW_TWD_BASE		0x10100700
-#define REALVIEW_TWD_SIZE		0x00000100
-#define REALVIEW_GIC_DIST_BASE		0x10101000	/* Generic interrupt controller distributor */
+#ifdef CONFIG_REALVIEW_MPCORE_REVB
+#define REALVIEW_MPCORE_SCU_BASE      0x10100000	/*  SCU registers */
+#define REALVIEW_GIC_CPU_BASE	      0x10100100	/* Generic interrupt controller CPU interface */
+#define REALVIEW_TWD_BASE	      0x10100700
+#define REALVIEW_GIC_DIST_BASE	      0x10101000	/* Generic interrupt controller distributor */
+#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8		/*  Register offset for MPCore sysctl */
+#else
+#define REALVIEW_MPCORE_SCU_BASE      0x1F000000	/*  SCU registers */
+#define REALVIEW_GIC_CPU_BASE	      0x1F000100	/* Generic interrupt controller CPU interface */
+#define REALVIEW_TWD_BASE	      0x1F000700
+#define REALVIEW_GIC_DIST_BASE	      0x1F001000	/* Generic interrupt controller distributor */
+#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74		/*  Register offset for MPCore sysctl */
+#endif
+#define REALVIEW_TWD_SIZE	      0x00000100
 #endif
 #define REALVIEW_SMC_BASE             0x10080000	/* SMC */
 	/* Reserved 0x10090000 - 0x100EFFFF */