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Commit 6780ccf5 authored by Sujith's avatar Sujith Committed by John W. Linville
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ath9k: Remove a few DEBUG mesages 

We have never used these at all.
Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent c16c9d06
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Showing with 23 additions and 103 deletions
drivers/net/wireless/ath/ath9k/eeprom.c
View file @ 6780ccf5
...@@ -236,9 +236,6 @@ static void ath9k_olc_get_pdadcs(struct ath_hw *ah, ...@@ -236,9 +236,6 @@ static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
pPDADCValues[i] = 0xFF; pPDADCValues[i] = 0xFF;
} }
static void ath9k_hw_get_target_powers(struct ath_hw *ah, static void ath9k_hw_get_target_powers(struct ath_hw *ah,
struct ath9k_channel *chan, struct ath9k_channel *chan,
struct cal_target_power_ht *powInfo, struct cal_target_power_ht *powInfo,
...@@ -905,20 +902,8 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, ...@@ -905,20 +902,8 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
ah->eep_ops->get_eeprom_rev(ah) <= 2) ah->eep_ops->get_eeprom_rev(ah) <= 2)
twiceMaxEdgePower = AR5416_MAX_RATE_POWER; twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
"EXT_ADDITIVE %d\n",
ctlMode, numCtlModes, isHt40CtlMode,
(pCtlMode[ctlMode] & EXT_ADDITIVE));
for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) && for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
pEepData->ctlIndex[i]; i++) { pEepData->ctlIndex[i]; i++) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
"pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
"chan %d\n",
i, cfgCtl, pCtlMode[ctlMode],
pEepData->ctlIndex[i], chan->channel);
if ((((cfgCtl & ~CTL_MODE_M) | if ((((cfgCtl & ~CTL_MODE_M) |
(pCtlMode[ctlMode] & CTL_MODE_M)) == (pCtlMode[ctlMode] & CTL_MODE_M)) ==
...@@ -936,13 +921,6 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, ...@@ -936,13 +921,6 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
IS_CHAN_2GHZ(chan), IS_CHAN_2GHZ(chan),
AR5416_EEP4K_NUM_BAND_EDGES); AR5416_EEP4K_NUM_BAND_EDGES);
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" MATCH-EE_IDX %d: ch %d is2 %d "
"2xMinEdge %d chainmask %d chains %d\n",
i, freq, IS_CHAN_2GHZ(chan),
twiceMinEdgePower, tx_chainmask,
ar5416_get_ntxchains
(tx_chainmask));
if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
twiceMaxEdgePower = twiceMaxEdgePower =
min(twiceMaxEdgePower, min(twiceMaxEdgePower,
...@@ -956,12 +934,6 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, ...@@ -956,12 +934,6 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" SEL-Min ctlMode %d pCtlMode %d "
"2xMaxEdge %d sP %d minCtlPwr %d\n",
ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
scaledPower, minCtlPower);
switch (pCtlMode[ctlMode]) { switch (pCtlMode[ctlMode]) {
case CTL_11B: case CTL_11B:
for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
...@@ -2491,20 +2463,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, ...@@ -2491,20 +2463,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
ah->eep_ops->get_eeprom_rev(ah) <= 2) ah->eep_ops->get_eeprom_rev(ah) <= 2)
twiceMaxEdgePower = AR5416_MAX_RATE_POWER; twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
"EXT_ADDITIVE %d\n",
ctlMode, numCtlModes, isHt40CtlMode,
(pCtlMode[ctlMode] & EXT_ADDITIVE));
for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
"pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
"chan %d\n",
i, cfgCtl, pCtlMode[ctlMode],
pEepData->ctlIndex[i], chan->channel);
if ((((cfgCtl & ~CTL_MODE_M) | if ((((cfgCtl & ~CTL_MODE_M) |
(pCtlMode[ctlMode] & CTL_MODE_M)) == (pCtlMode[ctlMode] & CTL_MODE_M)) ==
pEepData->ctlIndex[i]) || pEepData->ctlIndex[i]) ||
...@@ -2517,13 +2476,6 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, ...@@ -2517,13 +2476,6 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" MATCH-EE_IDX %d: ch %d is2 %d "
"2xMinEdge %d chainmask %d chains %d\n",
i, freq, IS_CHAN_2GHZ(chan),
twiceMinEdgePower, tx_chainmask,
ar5416_get_ntxchains
(tx_chainmask));
if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
twiceMaxEdgePower = min(twiceMaxEdgePower, twiceMaxEdgePower = min(twiceMaxEdgePower,
twiceMinEdgePower); twiceMinEdgePower);
...@@ -2536,12 +2488,6 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, ...@@ -2536,12 +2488,6 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
minCtlPower = min(twiceMaxEdgePower, scaledPower); minCtlPower = min(twiceMaxEdgePower, scaledPower);
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
" SEL-Min ctlMode %d pCtlMode %d "
"2xMaxEdge %d sP %d minCtlPwr %d\n",
ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
scaledPower, minCtlPower);
switch (pCtlMode[ctlMode]) { switch (pCtlMode[ctlMode]) {
case CTL_11B: case CTL_11B:
for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
...@@ -2898,17 +2844,15 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah) ...@@ -2898,17 +2844,15 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
if (!ath9k_hw_use_flash(ah)) { if (!ath9k_hw_use_flash(ah)) {
if (!ath9k_hw_nvram_read if (!ath9k_hw_nvram_read
(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
DPRINTF(ah->ah_sc, ATH_DBG_FATAL, DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Reading Magic # failed\n"); "Reading Magic # failed\n");
return false; return false;
} }
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"Read Magic = 0x%04X\n", magic); "Read Magic = 0x%04X\n", magic);
if (magic != AR5416_EEPROM_MAGIC) { if (magic != AR5416_EEPROM_MAGIC) {
magic2 = swab16(magic); magic2 = swab16(magic);
if (magic2 == AR5416_EEPROM_MAGIC) { if (magic2 == AR5416_EEPROM_MAGIC) {
...@@ -2924,13 +2868,14 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah) ...@@ -2924,13 +2868,14 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
} }
} else { } else {
DPRINTF(ah->ah_sc, ATH_DBG_FATAL, DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
"Invalid EEPROM Magic. " "Invalid EEPROM Magic. "
"endianness mismatch.\n"); "endianness mismatch.\n");
return -EINVAL; } return -EINVAL;
}
} }
} }
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ? DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ?
"True" : "False"); "True" : "False");
if (need_swap) if (need_swap)
el = swab16(ah->eeprom.map9287.baseEepHeader.length); el = swab16(ah->eeprom.map9287.baseEepHeader.length);
...@@ -3360,19 +3305,19 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah, ...@@ -3360,19 +3305,19 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
if (i == 0) { if (i == 0) {
if (!ath9k_hw_AR9287_get_eeprom( if (!ath9k_hw_AR9287_get_eeprom(
ah, EEP_OL_PWRCTRL)) { ah, EEP_OL_PWRCTRL)) {
REG_WRITE(ah, AR_PHY_TPCRG5 + REG_WRITE(ah, AR_PHY_TPCRG5 +
regChainOffset, regChainOffset,
SM(pdGainOverlap_t2, SM(pdGainOverlap_t2,
AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
SM(gainBoundaries[0], SM(gainBoundaries[0],
AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
| SM(gainBoundaries[1], | SM(gainBoundaries[1],
AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
| SM(gainBoundaries[2], | SM(gainBoundaries[2],
AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
| SM(gainBoundaries[3], | SM(gainBoundaries[3],
AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
} }
} }
...@@ -3394,6 +3339,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah, ...@@ -3394,6 +3339,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
pdadcValues[ pdadcValues[
AR9287_NUM_PDADC_VALUES-diff]; AR9287_NUM_PDADC_VALUES-diff];
} }
if (!ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { if (!ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
regOffset = AR_PHY_BASE + (672 << 2) + regOffset = AR_PHY_BASE + (672 << 2) +
regChainOffset; regChainOffset;
...@@ -3412,6 +3358,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah, ...@@ -3412,6 +3358,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
"PDADC (%d,%4x): %4.4x %8.8x\n", "PDADC (%d,%4x): %4.4x %8.8x\n",
i, regChainOffset, regOffset, i, regChainOffset, regOffset,
reg32); reg32);
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"PDADC: Chain %d | " "PDADC: Chain %d | "
"PDADC %3d Value %3d | " "PDADC %3d Value %3d | "
...@@ -3542,20 +3489,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah, ...@@ -3542,20 +3489,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
ah->eep_ops->get_eeprom_rev(ah) <= 2) ah->eep_ops->get_eeprom_rev(ah) <= 2)
twiceMaxEdgePower = AR5416_MAX_RATE_POWER; twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
"LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d,"
"EXT_ADDITIVE %d\n", ctlMode, numCtlModes,
isHt40CtlMode, (pCtlMode[ctlMode] & EXT_ADDITIVE));
for (i = 0; (i < AR9287_NUM_CTLS)
&& pEepData->ctlIndex[i]; i++) {
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"LOOP-Ctlidx %d: cfgCtl 0x%2.2x"
"pCtlMode 0x%2.2x ctlIndex 0x%2.2x"
"chan %d chanctl=xxxx\n",
i, cfgCtl, pCtlMode[ctlMode],
pEepData->ctlIndex[i], chan->channel);
if ((((cfgCtl & ~CTL_MODE_M) | if ((((cfgCtl & ~CTL_MODE_M) |
(pCtlMode[ctlMode] & CTL_MODE_M)) == (pCtlMode[ctlMode] & CTL_MODE_M)) ==
pEepData->ctlIndex[i]) || pEepData->ctlIndex[i]) ||
...@@ -3571,13 +3505,6 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah, ...@@ -3571,13 +3505,6 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
tx_chainmask) - 1], tx_chainmask) - 1],
IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"MATCH-EE_IDX %d: ch %d is2 %d"
"2xMinEdge %d chainmask %d chains %d\n",
i, freq, IS_CHAN_2GHZ(chan),
twiceMinEdgePower, tx_chainmask,
ar5416_get_ntxchains(tx_chainmask));
if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
twiceMaxEdgePower = min( twiceMaxEdgePower = min(
twiceMaxEdgePower, twiceMaxEdgePower,
...@@ -3591,14 +3518,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah, ...@@ -3591,14 +3518,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
"SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d"
"sP %d minCtlPwr %d\n",
ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
scaledPower, minCtlPower);
switch (pCtlMode[ctlMode]) { switch (pCtlMode[ctlMode]) {
case CTL_11B: case CTL_11B:
for (i = 0; for (i = 0;
i < ARRAY_SIZE(targetPowerCck.tPow2x); i < ARRAY_SIZE(targetPowerCck.tPow2x);
...@@ -3670,7 +3590,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah, ...@@ -3670,7 +3590,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
if (IS_CHAN_2GHZ(chan)) { if (IS_CHAN_2GHZ(chan)) {
ratesArray[rate1l] = targetPowerCck.tPow2x[0]; ratesArray[rate1l] = targetPowerCck.tPow2x[0];
ratesArray[rate2s] = ratesArray[rate2l] = ratesArray[rate2s] = ratesArray[rate2l] =
targetPowerCck.tPow2x[1]; targetPowerCck.tPow2x[1];
ratesArray[rate5_5s] = ratesArray[rate5_5l] = ratesArray[rate5_5s] = ratesArray[rate5_5l] =
...@@ -3686,7 +3606,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah, ...@@ -3686,7 +3606,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
if (IS_CHAN_2GHZ(chan)) if (IS_CHAN_2GHZ(chan))
ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
} }
#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN #undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
......
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