3430ES2 clock: Add several 3430ES2-only clocks

Add several OMAP3430ES2-only clocks:

- DPLL5, which provides clock to onboard USB and USIM modules;

- the Customer Programmable EFUSE;

- MMC3;

- SGX, the graphics module replacing GFX;

- the bandgap temperature sensor;

- USBHOST;

- USB TLL (transceiverless link);

- the Universal Subscriber Identity Module (USIM).

The interface clock for USB TLL is on CM_ICLKEN3, which formerly was
OMAP2430-only; so also convert OMAP2430_CM_ICLKEN3 to CM_ICLKEN3.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

arch/arm/mach-omap2/clock24xx.h

@@ -9,8 +9,8 @@
  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  *
- *  Copyright (C) 2007 Texas Instruments, Inc.
- *  Copyright (C) 2007 Nokia Corporation
+ *  Copyright (C) 2007-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2007-2008 Nokia Corporation
  *  Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
@@ -2311,7 +2311,7 @@ static struct clk sdrc_ick = {
 	.name		= "sdrc_ick",
 	.parent		= &l4_ck,
 	.flags		= CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
-	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP2430_CM_ICLKEN3),
+	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
 	.enable_bit	= OMAP2430_EN_SDRC_SHIFT,
 	.recalc		= &followparent_recalc,
 };

arch/arm/mach-omap2/cm.h

@@ -4,8 +4,8 @@
 /*
  * OMAP2/3 Clock Management (CM) register definitions
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -61,6 +61,7 @@ static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr)
 #define CM_ICLKEN1					0x0010
 #define CM_ICLKEN					CM_ICLKEN1
 #define CM_ICLKEN2					0x0014
+#define CM_ICLKEN3					0x0018
 #define CM_IDLEST1					0x0020
 #define CM_IDLEST                                       CM_IDLEST1
 #define CM_IDLEST2					0x0024
@@ -80,7 +81,6 @@ static u32 __attribute__((unused)) cm_read_reg(void __iomem *addr)
 #define OMAP24XX_CM_AUTOIDLE3				0x0038
 #define OMAP24XX_CM_AUTOIDLE4				0x003c
 
-#define OMAP2430_CM_ICLKEN3				0x0018
 #define OMAP2430_CM_IDLEST3				0x0028
 
 
@@ -110,6 +110,8 @@ static u32 __attribute__((unused)) cm_read_mod_reg(s16 module, s16 idx)
 #define OMAP_ST_GFX					(1 << 0)
 
 #define OMAP3430_CM_CLKEN_PLL				0x0004
+#define OMAP3430ES2_CM_CLKEN2				0x0004
+#define OMAP3430ES2_CM_FCLKEN3				0x0008
 #define OMAP3430_CM_IDLEST_PLL				CM_IDLEST2
 #define OMAP3430_CM_AUTOIDLE_PLL			CM_AUTOIDLE2
 #define OMAP3430_CM_CLKSEL1				CM_CLKSEL
@@ -118,6 +120,8 @@ static u32 __attribute__((unused)) cm_read_mod_reg(s16 module, s16 idx)
 #define OMAP3430_CM_SLEEPDEP				CM_CLKSEL2
 #define OMAP3430_CM_CLKSEL3				CM_CLKSTCTRL
 #define OMAP3430_CM_CLKSTST				0x004c
+#define OMAP3430ES2_CM_CLKSEL4				0x004c
+#define OMAP3430ES2_CM_CLKSEL5				0x0050
 #define OMAP3430_CM_CLKSEL2_EMU				0x0050
 #define OMAP3430_CM_CLKSEL3_EMU				0x0054
 

arch/arm/mach-omap2/cm_regbits_34xx.h

@@ -4,8 +4,8 @@
 /*
  * OMAP3430 Clock Management register bits
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -19,6 +19,8 @@
 /* Bits shared between registers */
 
 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
+#define OMAP3430ES2_EN_MMC3_MASK			(1 << 30)
+#define OMAP3430ES2_EN_MMC3_SHIFT			30
 #define OMAP3430_EN_MSPRO				(1 << 23)
 #define OMAP3430_EN_MSPRO_SHIFT				23
 #define OMAP3430_EN_HDQ					(1 << 22)
@@ -30,6 +32,10 @@
 #define OMAP3430_EN_SSI					(1 << 0)
 #define OMAP3430_EN_SSI_SHIFT				0
 
+/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
+#define OMAP3430ES2_EN_USBTLL_SHIFT			2
+#define OMAP3430ES2_EN_USBTLL_MASK			(1 << 2)
+
 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
 #define OMAP3430_EN_WDT2				(1 << 5)
 #define OMAP3430_EN_WDT2_SHIFT				5
@@ -165,6 +171,12 @@
 #define OMAP3430_EN_DES1				(1 << 0)
 #define OMAP3430_EN_DES1_SHIFT				0
 
+/* CM_FCLKEN3_CORE specific bits */
+#define OMAP3430ES2_EN_TS_SHIFT				1
+#define OMAP3430ES2_EN_TS_MASK				(1 << 1)
+#define OMAP3430ES2_EN_CPEFUSE_SHIFT			0
+#define OMAP3430ES2_EN_CPEFUSE_MASK			(1 << 0)
+
 /* CM_IDLEST1_CORE specific bits */
 #define OMAP3430_ST_ICR					(1 << 29)
 #define OMAP3430_ST_AES2				(1 << 28)
@@ -296,19 +308,28 @@
 /* CM_SLEEPDEP_GFX specific bits */
 
 /* CM_CLKSTCTRL_GFX */
-#define OMAP3430_CLKTRCTRL_GFX_SHIFT			0
-#define OMAP3430_CLKTRCTRL_GFX_MASK			(0x3 << 0)
+#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT			0
+#define OMAP3430ES1_CLKTRCTRL_GFX_MASK			(0x3 << 0)
 
 /* CM_CLKSTST_GFX */
-#define OMAP3430_CLKACTIVITY_GFX			(1 << 0)
+#define OMAP3430ES1_CLKACTIVITY_GFX			(1 << 0)
+
+/* CM_FCLKEN_SGX */
+#define OMAP3430ES2_EN_SGX_SHIFT			1
+#define OMAP3430ES2_EN_SGX_MASK				(1 << 1)
+
+/* CM_CLKSEL_SGX */
+#define OMAP3430ES2_CLKSEL_SGX_SHIFT			0
+#define OMAP3430ES2_CLKSEL_SGX_MASK			(0x7 << 0)
 
 /* CM_FCLKEN_WKUP specific bits */
+#define OMAP3430ES2_EN_USIMOCP_SHIFT			9
 
 /* CM_ICLKEN_WKUP specific bits */
 #define OMAP3430_EN_WDT1				(1 << 4)
 #define OMAP3430_EN_WDT1_SHIFT				4
 #define OMAP3430_EN_32KSYNC				(1 << 2)
-#define OMAP3430_EN_32KSYNC_SHIFT			       2
+#define OMAP3430_EN_32KSYNC_SHIFT			2
 
 /* CM_IDLEST_WKUP specific bits */
 #define OMAP3430_ST_WDT2				(1 << 5)
@@ -330,10 +351,11 @@
 #define OMAP3430_AUTO_GPT1_SHIFT			0
 
 /* CM_CLKSEL_WKUP */
+#define OMAP3430ES2_CLKSEL_USIMOCP_MASK			(0xf << 3)
 #define OMAP3430_CLKSEL_RM_SHIFT			1
 #define OMAP3430_CLKSEL_RM_MASK				(0x3 << 1)
-#define OMAP3430_CLKSEL_GPT1_MASK			(1 << 0)
 #define OMAP3430_CLKSEL_GPT1_SHIFT			0
+#define OMAP3430_CLKSEL_GPT1_MASK			(1 << 0)
 
 /* CM_CLKEN_PLL */
 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT			31
@@ -359,6 +381,13 @@
 #define OMAP3430_EN_CORE_DPLL_SHIFT			0
 #define OMAP3430_EN_CORE_DPLL_MASK			(0x7 << 0)
 
+/* CM_CLKEN2_PLL */
+#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT		10
+#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK		(0x3 << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK		(0xf << 4)
+#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT	3
+#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK		        (0x7 << 0)
+
 /* CM_IDLEST_CKGEN */
 #define OMAP3430_ST_54M_CLK				(1 << 5)
 #define OMAP3430_ST_12M_CLK				(1 << 4)
@@ -394,6 +423,13 @@
 #define OMAP3430_DIV_96M_SHIFT				0
 #define OMAP3430_DIV_96M_MASK				(0x1f << 0)
 
+/* CM_CLKSEL4_PLL */
+#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK		(0x7ff << 8)
+#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK		(0x7f << 0)
+
+/* CM_CLKSEL5_PLL */
+#define OMAP3430ES2_DIV_120M_MASK			(0x1f << 0)
+
 /* CM_CLKOUT_CTRL */
 #define OMAP3430_CLKOUT2_EN_SHIFT			7
 #define OMAP3430_CLKOUT2_EN				(1 << 7)
@@ -583,4 +619,14 @@
 #define OMAP3430_CLKTRCTRL_NEON_SHIFT			0
 #define OMAP3430_CLKTRCTRL_NEON_MASK			(0x3 << 0)
 
+/* CM_FCLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST2_SHIFT			1
+#define OMAP3430ES2_EN_USBHOST2_MASK			(1 << 1)
+#define OMAP3430ES2_EN_USBHOST1_SHIFT			0
+#define OMAP3430ES2_EN_USBHOST1_MASK			(1 << 0)
+
+/* CM_ICLKEN_USBHOST */
+#define OMAP3430ES2_EN_USBHOST_SHIFT			0
+#define OMAP3430ES2_EN_USBHOST_MASK			(1 << 0)
+
 #endif

arch/arm/mach-omap2/prcm_common.h

@@ -4,8 +4,8 @@
 /*
  * OMAP2/3 PRCM base and module definitions
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -17,8 +17,12 @@
 
 /* Module offsets from both CM_BASE & PRM_BASE */
 
-/* Offsets that are the same on 24xx and 34xx */
-/* Technically OCP_MOD is 34xx only, and PLL_MOD is CCR_MOD on 3430 */
+/*
+ * Offsets that are the same on 24xx and 34xx
+ *
+ * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
+ * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
+ */
 #define OCP_MOD						0x000
 #define MPU_MOD						0x100
 #define CORE_MOD					0x200
@@ -34,6 +38,7 @@
 
 /* IVA2 module is < base on 3430 */
 #define OMAP3430_IVA2_MOD				-0x800
+#define OMAP3430ES2_SGX_MOD				GFX_MOD
 #define OMAP3430_CCR_MOD				PLL_MOD
 #define OMAP3430_DSS_MOD				0x600
 #define OMAP3430_CAM_MOD				0x700
@@ -41,6 +46,7 @@
 #define OMAP3430_EMU_MOD				0x900
 #define OMAP3430_GR_MOD					0xa00
 #define OMAP3430_NEON_MOD				0xb00
+#define OMAP3430ES2_USBHOST_MOD				0xc00
 
 
 /* 24XX register bits shared between CM & PRM registers */

arch/arm/mach-omap2/prm_regbits_34xx.h

@@ -4,8 +4,8 @@
 /*
  * OMAP3430 Power/Reset Management register bits
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -211,6 +211,8 @@
 /* PRM_SYSCONFIG specific bits */
 
 /* PRM_IRQSTATUS_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT		25
+#define OMAP3430ES2_SND_PERIPH_DPLL_ST			(1 << 25)
 #define OMAP3430_VC_TIMEOUTERR_ST			(1 << 24)
 #define OMAP3430_VC_RAERR_ST				(1 << 23)
 #define OMAP3430_VC_SAERR_ST				(1 << 22)
@@ -241,6 +243,8 @@
 #define OMAP3430_FS_USB_WKUP_ST				(1 << 1)
 
 /* PRM_IRQENABLE_MPU specific bits */
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT		25
+#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN			(1 << 25)
 #define OMAP3430_VC_TIMEOUTERR_EN				(1 << 24)
 #define OMAP3430_VC_RAERR_EN					(1 << 23)
 #define OMAP3430_VC_SAERR_EN					(1 << 22)
@@ -400,6 +404,9 @@
 
 /* PM_PREPWSTST_CAM specific bits */
 
+/* PM_PWSTCTRL_USBHOST specific bits */
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT		(1 << 4)
+
 /* RM_RSTST_PER specific bits */
 
 /* PM_WKEN_PER specific bits */