Add support for the new Cache ID format in ARMv7

This patch renames the old __cacheid_* macros to __cacheid_*_prev7 and adds
support for the new format.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

include/asm-arm/cacheflush.h

@@ -348,11 +348,23 @@ extern void flush_dcache_page(struct page *);
  */
 #define flush_icache_page(vma,page)	do { } while (0)
 
-#define __cacheid_present(val)		(val != read_cpuid(CPUID_ID))
-#define __cacheid_vivt(val)		((val & (15 << 25)) != (14 << 25))
-#define __cacheid_vipt(val)		((val & (15 << 25)) == (14 << 25))
-#define __cacheid_vipt_nonaliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25))
-#define __cacheid_vipt_aliasing(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
+#define __cacheid_present(val)			(val != read_cpuid(CPUID_ID))
+#define __cacheid_type_v7(val)			(val & (1 << 31))
+
+#define __cacheid_vivt_prev7(val)		((val & (15 << 25)) != (14 << 25))
+#define __cacheid_vipt_prev7(val)		((val & (15 << 25)) == (14 << 25))
+#define __cacheid_vipt_nonaliasing_prev7(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25))
+#define __cacheid_vipt_aliasing_prev7(val)	((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
+
+#define __cacheid_vivt_v7(val)			((val & (3 << 14)) == 1)
+#define __cacheid_vipt_v7(val)			((val & (2 << 14)) != 0)
+#define __cacheid_vipt_nonaliasing_v7(val)	1
+#define __cacheid_vipt_aliasing_v7(val)		0
+
+#define __cacheid_vivt(val)			(__cacheid_type_v7(val) ? __cacheid_vivt_v7(val) : __cacheid_vivt_prev7(val))
+#define __cacheid_vipt(val)			(__cacheid_type_v7(val) ? __cacheid_vipt_v7(val) : __cacheid_vipt_prev7(val))
+#define __cacheid_vipt_nonaliasing(val)		(__cacheid_type_v7(val) ? __cacheid_vipt_nonaliasing_v7(val) : __cacheid_vipt_nonaliasing_prev7(val))
+#define __cacheid_vipt_aliasing(val)		(__cacheid_type_v7(val) ? __cacheid_vipt_aliasing_v7(val) : __cacheid_vipt_aliasing_prev7(val))
 
 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)