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Commit 5b9799c8 authored by Tony Lindgren's avatar Tony Lindgren
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musb_hdrc: Search and replace wCsrVal with csr 

Search and replace wCsrVal with csr
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent ba4cd005
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Showing with 114 additions and 114 deletions
drivers/usb/musb/g_ep0.c
View file @ 5b9799c8
......@@ -485,7 +485,7 @@ static void ep0_txstate(struct musb *musb)
{
void __iomem *regs = musb->control_ep->regs;
struct usb_request *request = next_ep0_request(musb);
u16 wCsrVal = MGC_M_CSR0_TXPKTRDY;
u16 csr = MGC_M_CSR0_TXPKTRDY;
u8 *pFifoSource;
u8 fifo_count;
......@@ -506,12 +506,12 @@ static void ep0_txstate(struct musb *musb)
if (fifo_count < MUSB_MAX_END0_PACKET
|| request->actual == request->length) {
musb->ep0_state = MGC_END0_STAGE_STATUSOUT;
wCsrVal |= MGC_M_CSR0_P_DATAEND;
csr |= MGC_M_CSR0_P_DATAEND;
} else
request = NULL;
/* send it out, triggering a "txpktrdy cleared" irq */
musb_writew(regs, MGC_O_HDRC_CSR0, wCsrVal);
musb_writew(regs, MGC_O_HDRC_CSR0, csr);
/* report completions as soon as the fifo's loaded; there's no
* win in waiting till this last packet gets acked. (other than
......@@ -598,36 +598,36 @@ __acquires(musb->lock)
*/
irqreturn_t musb_g_ep0_irq(struct musb *musb)
{
u16 wCsrVal;
u16 csr;
u16 len;
void __iomem *mbase = musb->mregs;
void __iomem *regs = musb->endpoints[0].regs;
irqreturn_t retval = IRQ_NONE;
musb_ep_select(mbase, 0); /* select ep0 */
wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
csr = musb_readw(regs, MGC_O_HDRC_CSR0);
len = musb_readb(regs, MGC_O_HDRC_COUNT0);
DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
wCsrVal, len,
csr, len,
musb_readb(mbase, MGC_O_HDRC_FADDR),
decode_ep0stage(musb->ep0_state));
/* I sent a stall.. need to acknowledge it now.. */
if (wCsrVal & MGC_M_CSR0_P_SENTSTALL) {
if (csr & MGC_M_CSR0_P_SENTSTALL) {
musb_writew(regs, MGC_O_HDRC_CSR0,
wCsrVal & ~MGC_M_CSR0_P_SENTSTALL);
csr & ~MGC_M_CSR0_P_SENTSTALL);
retval = IRQ_HANDLED;
musb->ep0_state = MGC_END0_STAGE_SETUP;
wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
csr = musb_readw(regs, MGC_O_HDRC_CSR0);
}
/* request ended "early" */
if (wCsrVal & MGC_M_CSR0_P_SETUPEND) {
if (csr & MGC_M_CSR0_P_SETUPEND) {
musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDSETUPEND);
retval = IRQ_HANDLED;
musb->ep0_state = MGC_END0_STAGE_SETUP;
wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
csr = musb_readw(regs, MGC_O_HDRC_CSR0);
/* NOTE: request may need completion */
}
......@@ -639,7 +639,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
case MGC_END0_STAGE_TX:
/* irq on clearing txpktrdy */
if ((wCsrVal & MGC_M_CSR0_TXPKTRDY) == 0) {
if ((csr & MGC_M_CSR0_TXPKTRDY) == 0) {
ep0_txstate(musb);
retval = IRQ_HANDLED;
}
......@@ -647,7 +647,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
case MGC_END0_STAGE_RX:
/* irq on set rxpktrdy */
if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
if (csr & MGC_M_CSR0_RXPKTRDY) {
ep0_rxstate(musb);
retval = IRQ_HANDLED;
}
......@@ -692,7 +692,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
/* FALLTHROUGH */
case MGC_END0_STAGE_SETUP:
if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
if (csr & MGC_M_CSR0_RXPKTRDY) {
struct usb_ctrlrequest setup;
int handled = 0;
......@@ -755,7 +755,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
}
DBG(3, "handled %d, csr %04x, ep0stage %s\n",
handled, wCsrVal,
handled, csr,
decode_ep0stage(musb->ep0_state));
/* unless we need to delegate this to the gadget
......
drivers/usb/musb/musb_gadget.c
View file @ 5b9799c8
This diff is collapsed.
drivers/usb/musb/musb_host.c
View file @ 5b9799c8
......@@ -1021,7 +1021,7 @@ static int musb_h_ep0_continue(struct musb *musb,
irqreturn_t musb_h_ep0_irq(struct musb *musb)
{
struct urb *pUrb;
u16 wCsrVal, len;
u16 csr, len;
int status = 0;
void __iomem *mbase = musb->mregs;
struct musb_hw_ep *hw_ep = musb->control_ep;
......@@ -1034,13 +1034,13 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
pUrb = next_urb(qh);
musb_ep_select(mbase, 0);
wCsrVal = musb_readw(epio, MGC_O_HDRC_CSR0);
len = (wCsrVal & MGC_M_CSR0_RXPKTRDY)
csr = musb_readw(epio, MGC_O_HDRC_CSR0);
len = (csr & MGC_M_CSR0_RXPKTRDY)
? musb_readb(epio, MGC_O_HDRC_COUNT0)
: 0;
DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
wCsrVal, qh, len, pUrb, musb->ep0_stage);
csr, qh, len, pUrb, musb->ep0_stage);
/* if we just did status stage, we are done */
if (MGC_END0_STATUS == musb->ep0_stage) {
......@@ -1049,15 +1049,15 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
}
/* prepare status */
if (wCsrVal & MGC_M_CSR0_H_RXSTALL) {
if (csr & MGC_M_CSR0_H_RXSTALL) {
DBG(6, "STALLING ENDPOINT\n");
status = -EPIPE;
} else if (wCsrVal & MGC_M_CSR0_H_ERROR) {
DBG(2, "no response, csr0 %04x\n", wCsrVal);
} else if (csr & MGC_M_CSR0_H_ERROR) {
DBG(2, "no response, csr0 %04x\n", csr);
status = -EPROTO;
} else if (wCsrVal & MGC_M_CSR0_H_NAKTIMEOUT) {
} else if (csr & MGC_M_CSR0_H_NAKTIMEOUT) {
DBG(2, "control NAK timeout\n");
/* NOTE: this code path would be a good place to PAUSE a
......@@ -1079,17 +1079,17 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
bComplete = TRUE;
/* use the proper sequence to abort the transfer */
if (wCsrVal & MGC_M_CSR0_H_REQPKT) {
wCsrVal &= ~MGC_M_CSR0_H_REQPKT;
musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
wCsrVal &= ~MGC_M_CSR0_H_NAKTIMEOUT;
musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
if (csr & MGC_M_CSR0_H_REQPKT) {
csr &= ~MGC_M_CSR0_H_REQPKT;
musb_writew(epio, MGC_O_HDRC_CSR0, csr);
csr &= ~MGC_M_CSR0_H_NAKTIMEOUT;
musb_writew(epio, MGC_O_HDRC_CSR0, csr);
} else {
wCsrVal |= MGC_M_CSR0_FLUSHFIFO;
musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
wCsrVal &= ~MGC_M_CSR0_H_NAKTIMEOUT;
musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
csr |= MGC_M_CSR0_FLUSHFIFO;
musb_writew(epio, MGC_O_HDRC_CSR0, csr);
musb_writew(epio, MGC_O_HDRC_CSR0, csr);
csr &= ~MGC_M_CSR0_H_NAKTIMEOUT;
musb_writew(epio, MGC_O_HDRC_CSR0, csr);
}
musb_writeb(epio, MGC_O_HDRC_NAKLIMIT0, 0);
......@@ -1114,25 +1114,25 @@ irqreturn_t musb_h_ep0_irq(struct musb *musb)
/* call common logic and prepare response */
if (musb_h_ep0_continue(musb, len, pUrb)) {
/* more packets required */
wCsrVal = (MGC_END0_IN == musb->ep0_stage)
csr = (MGC_END0_IN == musb->ep0_stage)
? MGC_M_CSR0_H_REQPKT : MGC_M_CSR0_TXPKTRDY;
} else {
/* data transfer complete; perform status phase */
if (usb_pipeout(pUrb->pipe)
|| !pUrb->transfer_buffer_length)
wCsrVal = MGC_M_CSR0_H_STATUSPKT
csr = MGC_M_CSR0_H_STATUSPKT
| MGC_M_CSR0_H_REQPKT;
else
wCsrVal = MGC_M_CSR0_H_STATUSPKT
csr = MGC_M_CSR0_H_STATUSPKT
| MGC_M_CSR0_TXPKTRDY;
/* flag status stage */
musb->ep0_stage = MGC_END0_STATUS;
DBG(5, "ep0 STATUS, csr %04x\n", wCsrVal);
DBG(5, "ep0 STATUS, csr %04x\n", csr);
}
musb_writew(epio, MGC_O_HDRC_CSR0, wCsrVal);
musb_writew(epio, MGC_O_HDRC_CSR0, csr);
retval = IRQ_HANDLED;
} else
musb->ep0_stage = MGC_END0_IDLE;
......
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