[ARM] 3796/1: S3C24XX: Add per-cpu DMA channel mapper

Allow each CPU type in the S3C24XX range to
select the DMA channel mapping it supports.

We change the DMA registration to use an
virtual channel number that the DMA system
will allocate to a hardware channel at
request time.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mach-s3c2410/Makefile

@@ -9,6 +9,8 @@ obj-y			:= cpu.o irq.o time.o gpio.o clock.o devs.o
 obj-m			:=
 obj-n			:=
 obj-			:=
+obj-dma-y		:=
+obj-dma-n		:=
 
 # DMA
 obj-$(CONFIG_S3C2410_DMA)	+= dma.o
@@ -57,6 +59,10 @@ obj-$(CONFIG_CPU_S3C2442)	+= s3c2442-clock.o
 
 obj-$(CONFIG_BAST_PC104_IRQ)	+= bast-irq.o
 
+# merge in dma objects
+
+obj-y				+= $(obj-dma-y)
+
 # machine specific support
 
 obj-$(CONFIG_MACH_ANUBIS)	+= mach-anubis.o

arch/arm/mach-s3c2410/dma.h

+/* arch/arm/mach-s3c2410/dma.h
+ *
+ * Copyright (C) 2006 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C24XX DMA support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+extern struct sysdev_class dma_sysclass;
+extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
+
+#define DMA_CH_VALID		(1<<31)
+
+struct s3c24xx_dma_addr {
+	unsigned long		from;
+	unsigned long		to;
+};
+
+/* struct s3c24xx_dma_map
+ *
+ * this holds the mapping information for the channel selected
+ * to be connected to the specified device
+*/
+
+struct s3c24xx_dma_map {
+	const char		*name;
+	struct s3c24xx_dma_addr  hw_addr;
+
+	unsigned long		 channels[S3C2410_DMA_CHANNELS];
+};
+
+struct s3c24xx_dma_selection {
+	struct s3c24xx_dma_map	*map;
+	unsigned long		 map_size;
+	unsigned long		 dcon_mask;
+
+	void	(*select)(struct s3c2410_dma_chan *chan,
+			  struct s3c24xx_dma_map *map);
+};
+
+extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);

include/asm-arm/arch-s3c2410/dma.h

@@ -23,6 +23,36 @@
 #define MAX_DMA_ADDRESS		0x40000000
 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
 
+/* We use `virtual` dma channels to hide the fact we have only a limited
+ * number of DMA channels, and not of all of them (dependant on the device)
+ * can be attached to any DMA source. We therefore let the DMA core handle
+ * the allocation of hardware channels to clients.
+*/
+
+enum dma_ch {
+	DMACH_XD0,
+	DMACH_XD1,
+	DMACH_SDI,
+	DMACH_SPI0,
+	DMACH_SPI1,
+	DMACH_UART0,
+	DMACH_UART1,
+	DMACH_UART2,
+	DMACH_TIMER,
+	DMACH_I2S_IN,
+	DMACH_I2S_OUT,
+	DMACH_PCM_IN,
+	DMACH_PCM_OUT,
+	DMACH_MIC_IN,
+	DMACH_USB_EP1,
+	DMACH_USB_EP2,
+	DMACH_USB_EP3,
+	DMACH_USB_EP4,
+	DMACH_MAX,		/* the end entry */
+};
+
+#define DMACH_LOW_LEVEL	(1<<28)	/* use this to specifiy hardware ch no */
+
 /* we have 4 dma channels */
 #define S3C2410_DMA_CHANNELS        (4)
 
@@ -149,6 +179,8 @@ struct s3c2410_dma_stats {
 	unsigned long		timeout_failed;
 };
 
+struct s3c2410_dma_map;
+
 /* struct s3c2410_dma_chan
  *
  * full state information for each DMA channel
@@ -174,6 +206,8 @@ struct s3c2410_dma_chan {
 	unsigned long		 load_timeout;
 	unsigned int		 flags;		/* channel flags */
 
+	struct s3c24xx_dma_map	*map;		/* channel hw maps */
+
 	/* channel's hardware position and configuration */
 	void __iomem		*regs;		/* channels registers */
 	void __iomem		*addr_reg;	/* data address register */