Commit 4af9cf4f authored by Sujith's avatar Sujith Committed by John W. Linville

ath9k: Enable TSF Out of Range Interrupt

This patch lays the groundwork for handling TSF Out of Range
interrupt, which will be used for power save later on.
Signed-off-by: default avatarSujith <Sujith.Manoharan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 06d0f066
...@@ -753,6 +753,9 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ...@@ -753,6 +753,9 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
if (bs.bs_sleepduration > bs.bs_dtimperiod) if (bs.bs_sleepduration > bs.bs_dtimperiod)
bs.bs_sleepduration = bs.bs_dtimperiod; bs.bs_sleepduration = bs.bs_dtimperiod;
/* TSF out of range threshold fixed at 1 second */
bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
DPRINTF(sc, ATH_DBG_BEACON, DPRINTF(sc, ATH_DBG_BEACON,
"tsf %llu " "tsf %llu "
"tsf:tu %u " "tsf:tu %u "
......
...@@ -2803,6 +2803,8 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) ...@@ -2803,6 +2803,8 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
mask2 |= ATH9K_INT_GTT; mask2 |= ATH9K_INT_GTT;
if (isr2 & AR_ISR_S2_CST) if (isr2 & AR_ISR_S2_CST)
mask2 |= ATH9K_INT_CST; mask2 |= ATH9K_INT_CST;
if (isr2 & AR_ISR_S2_TSFOOR)
mask2 |= ATH9K_INT_TSFOOR;
} }
isr = REG_READ(ah, AR_ISR_RAC); isr = REG_READ(ah, AR_ISR_RAC);
...@@ -2948,7 +2950,9 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) ...@@ -2948,7 +2950,9 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
if (ints & ATH9K_INT_DTIMSYNC) if (ints & ATH9K_INT_DTIMSYNC)
mask2 |= AR_IMR_S2_DTIMSYNC; mask2 |= AR_IMR_S2_DTIMSYNC;
if (ints & ATH9K_INT_CABEND) if (ints & ATH9K_INT_CABEND)
mask2 |= (AR_IMR_S2_CABEND); mask2 |= AR_IMR_S2_CABEND;
if (ints & ATH9K_INT_TSFOOR)
mask2 |= AR_IMR_S2_TSFOOR;
} }
if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
...@@ -3118,6 +3122,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, ...@@ -3118,6 +3122,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
AR_DTIM_TIMER_EN); AR_DTIM_TIMER_EN);
/* TSF Out of Range Threshold */
REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
} }
/*******************/ /*******************/
......
...@@ -249,6 +249,7 @@ enum ath9k_int { ...@@ -249,6 +249,7 @@ enum ath9k_int {
ATH9K_INT_DTIMSYNC = 0x00800000, ATH9K_INT_DTIMSYNC = 0x00800000,
ATH9K_INT_GPIO = 0x01000000, ATH9K_INT_GPIO = 0x01000000,
ATH9K_INT_CABEND = 0x02000000, ATH9K_INT_CABEND = 0x02000000,
ATH9K_INT_TSFOOR = 0x04000000,
ATH9K_INT_CST = 0x10000000, ATH9K_INT_CST = 0x10000000,
ATH9K_INT_GTT = 0x20000000, ATH9K_INT_GTT = 0x20000000,
ATH9K_INT_FATAL = 0x40000000, ATH9K_INT_FATAL = 0x40000000,
...@@ -256,6 +257,7 @@ enum ath9k_int { ...@@ -256,6 +257,7 @@ enum ath9k_int {
ATH9K_INT_BMISC = ATH9K_INT_TIM | ATH9K_INT_BMISC = ATH9K_INT_TIM |
ATH9K_INT_DTIM | ATH9K_INT_DTIM |
ATH9K_INT_DTIMSYNC | ATH9K_INT_DTIMSYNC |
ATH9K_INT_TSFOOR |
ATH9K_INT_CABEND, ATH9K_INT_CABEND,
ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
ATH9K_INT_RXDESC | ATH9K_INT_RXDESC |
...@@ -385,6 +387,7 @@ struct ath9k_beacon_state { ...@@ -385,6 +387,7 @@ struct ath9k_beacon_state {
#define ATH9K_BEACON_PERIOD 0x0000ffff #define ATH9K_BEACON_PERIOD 0x0000ffff
#define ATH9K_BEACON_ENA 0x00800000 #define ATH9K_BEACON_ENA 0x00800000
#define ATH9K_BEACON_RESET_TSF 0x01000000 #define ATH9K_BEACON_RESET_TSF 0x01000000
#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
u32 bs_dtimperiod; u32 bs_dtimperiod;
u16 bs_cfpperiod; u16 bs_cfpperiod;
u16 bs_cfpmaxduration; u16 bs_cfpmaxduration;
...@@ -392,6 +395,7 @@ struct ath9k_beacon_state { ...@@ -392,6 +395,7 @@ struct ath9k_beacon_state {
u16 bs_timoffset; u16 bs_timoffset;
u16 bs_bmissthreshold; u16 bs_bmissthreshold;
u32 bs_sleepduration; u32 bs_sleepduration;
u32 bs_tsfoor_threshold;
}; };
struct chan_centers { struct chan_centers {
......
...@@ -574,6 +574,10 @@ irqreturn_t ath_isr(int irq, void *dev) ...@@ -574,6 +574,10 @@ irqreturn_t ath_isr(int irq, void *dev)
sc->sc_flags |= SC_OP_WAIT_FOR_BEACON; sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
} }
} }
if (status & ATH9K_INT_TSFOOR) {
/* FIXME: Handle this interrupt for power save */
sched = true;
}
} }
} while (0); } while (0);
...@@ -2165,10 +2169,13 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, ...@@ -2165,10 +2169,13 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
* Enable MIB interrupts when there are hardware phy counters. * Enable MIB interrupts when there are hardware phy counters.
* Note we only do this (at the moment) for station mode. * Note we only do this (at the moment) for station mode.
*/ */
if (ath9k_hw_phycounters(sc->sc_ah) && if ((conf->type == NL80211_IFTYPE_STATION) ||
((conf->type == NL80211_IFTYPE_STATION) || (conf->type == NL80211_IFTYPE_ADHOC)) {
(conf->type == NL80211_IFTYPE_ADHOC))) if (ath9k_hw_phycounters(sc->sc_ah))
sc->imask |= ATH9K_INT_MIB; sc->imask |= ATH9K_INT_MIB;
sc->imask |= ATH9K_INT_TSFOOR;
}
/* /*
* Some hardware processes the TIM IE and fires an * Some hardware processes the TIM IE and fires an
* interrupt when the TIM bit is set. For hardware * interrupt when the TIM bit is set. For hardware
......
...@@ -1385,8 +1385,8 @@ enum { ...@@ -1385,8 +1385,8 @@ enum {
#define AR_PHY_COUNTMAX (3 << 22) #define AR_PHY_COUNTMAX (3 << 22)
#define AR_MIBCNT_INTRMASK (3 << 22) #define AR_MIBCNT_INTRMASK (3 << 22)
#define AR_TSF_THRESHOLD 0x813c #define AR_TSFOOR_THRESHOLD 0x813c
#define AR_TSF_THRESHOLD_VAL 0x0000FFFF #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF
#define AR_PHY_ERR_EIFS_MASK 8144 #define AR_PHY_ERR_EIFS_MASK 8144
......
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