Commit 48c72fcc authored by Magnus Damm's avatar Magnus Damm Committed by Paul Mundt

sh: 16-bit get_unaligned() sh4a fix

This patch fixes the 16-bit case of the sh4a specific
unaligned access implementation. Without this patch
the 16-bit version of sh4a get_unaligned() results in
a 32-bit read which may read more data than intended
and/or cross page boundaries.

Unbreaks mtd NOR write handling on Migo-R.
Signed-off-by: default avatarMagnus Damm <damm@igel.co.jp>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 138f0252
...@@ -3,9 +3,9 @@ ...@@ -3,9 +3,9 @@
/* /*
* SH-4A has support for unaligned 32-bit loads, and 32-bit loads only. * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
* Support for 16 and 64-bit accesses are done through shifting and * Support for 64-bit accesses are done through shifting and masking
* masking relative to the endianness. Unaligned stores are not supported * relative to the endianness. Unaligned stores are not supported by the
* by the instruction encoding, so these continue to use the packed * instruction encoding, so these continue to use the packed
* struct. * struct.
* *
* The same note as with the movli.l/movco.l pair applies here, as long * The same note as with the movli.l/movco.l pair applies here, as long
...@@ -41,9 +41,9 @@ struct __una_u64 { u64 x __attribute__((packed)); }; ...@@ -41,9 +41,9 @@ struct __una_u64 { u64 x __attribute__((packed)); };
static inline u16 __get_unaligned_cpu16(const u8 *p) static inline u16 __get_unaligned_cpu16(const u8 *p)
{ {
#ifdef __LITTLE_ENDIAN #ifdef __LITTLE_ENDIAN
return __get_unaligned_cpu32(p) & 0xffff; return p[0] | p[1] << 8;
#else #else
return __get_unaligned_cpu32(p) >> 16; return p[0] << 8 | p[1];
#endif #endif
} }
......
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