Add noMMU support for ARMv7

This patch adds the necessary ifdef's to the code.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

arch/arm/mm/proc-v7.S

@@ -77,6 +77,7 @@ ENTRY(cpu_v7_dcache_clean_area)
  *	- we are not using split page tables
  */
 ENTRY(cpu_v7_switch_mm)
+#ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
 	orr	r0, r0, #TTB_RGN_OC_WB		@ mark PTWs outer cacheable, WB
@@ -86,6 +87,7 @@ ENTRY(cpu_v7_switch_mm)
 	isb
 	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
 	isb
+#endif
 	mov	pc, lr
 
 /*
@@ -108,6 +110,7 @@ ENTRY(cpu_v7_switch_mm)
  *	  1111   0   1   1	r/w	r/w
  */
 ENTRY(cpu_v7_set_pte)
+#ifdef CONFIG_MMU
 	str	r1, [r0], #-2048		@ linux version
 
 	bic	r2, r1, #0x000007f0
@@ -135,6 +138,7 @@ ENTRY(cpu_v7_set_pte)
 	str	r2, [r0]
 	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
 	dsb
+#endif
 	mov	pc, lr
 
 cpu_v7_name:
@@ -168,6 +172,7 @@ __v7_setup:
 	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
 #endif
 	dsb
+#ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
 	orr	r4, r4, #TTB_RGN_OC_WB		@ mark PTWs outer cacheable, WB
@@ -175,6 +180,7 @@ __v7_setup:
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
+#endif
 #ifndef CONFIG_CPU_L2CACHE_DISABLE
 	@ L2 cache configuration in the L2 aux control register
 	mrc	p15, 1, r10, c9, c0, 2
@@ -185,11 +191,11 @@ __v7_setup:
 	orr	r10, r10, #2
 	mcr	p15, 0, r10, c1, c0, 1
 #endif
+	adr	r5, v7_crval
+	ldmia	r5, {r5, r6}
    	mrc	p15, 0, r0, c1, c0, 0		@ read control register
-	ldr	r10, cr1_clear			@ get mask for bits to clear
-	bic	r0, r0, r10			@ clear bits them
-	ldr	r10, cr1_set			@ get mask for bits to set
-	orr	r0, r0, r10			@ set them
+	bic	r0, r0, r5			@ clear bits them
+	orr	r0, r0, r6			@ set them
 	mov	pc, lr				@ return to head.S:__ret
 
 	/*
@@ -198,12 +204,9 @@ __v7_setup:
 	 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
 	 *         0 110       0011 1.00 .111 1101 < we want
 	 */
-	.type	cr1_clear, #object
-	.type	cr1_set, #object
-cr1_clear:
-	.word	0x0120c302
-cr1_set:
-	.word	0x00c0387d
+	.type	v7_crval, #object
+v7_crval:
+	crval	clear=0x0120f306, mmuset=0x00c0387d, ucset=0x00c0187c
 
 __v7_setup_stack:
 	.space	4 * 11				@ 11 registers
@@ -256,7 +259,9 @@ __v7_proc_info:
 	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 	.long	cpu_v7_name
 	.long	v7_processor_functions
+#ifdef CONFIG_MMU
 	.long	v7wbi_tlb_fns
+#endif
 	.long	v6_user_fns
 	.long	v7_cache_fns
 	.size	__v7_proc_info, . - __v7_proc_info