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Commit 38c50a71 authored by Tony Lindgren's avatar Tony Lindgren
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ARM: OMAP: Clean up interrupt lines to fix warning for multi-omap 

If boards with different NR_IRQS are compiled together, tons of
compiler warnings are emitted about redefining NR_IRQS.

This patch fixes the problem by adding up NR_IRQS in a common place.

Patch also removes quite a bit of now unnecessary code.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent c310c979
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Inline Side-by-side
Showing with 97 additions and 182 deletions
arch/arm/mach-omap1/fpga.c
View file @ 38c50a71
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
static void fpga_mask_irq(unsigned int irq) static void fpga_mask_irq(unsigned int irq)
{ {
irq -= OMAP1510_IH_FPGA_BASE; irq -= OMAP_FPGA_IRQ_BASE;
if (irq < 8) if (irq < 8)
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
...@@ -65,7 +65,7 @@ static void fpga_ack_irq(unsigned int irq) ...@@ -65,7 +65,7 @@ static void fpga_ack_irq(unsigned int irq)
static void fpga_unmask_irq(unsigned int irq) static void fpga_unmask_irq(unsigned int irq)
{ {
irq -= OMAP1510_IH_FPGA_BASE; irq -= OMAP_FPGA_IRQ_BASE;
if (irq < 8) if (irq < 8)
__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)), __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
...@@ -95,8 +95,8 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc) ...@@ -95,8 +95,8 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
if (!stat) if (!stat)
return; return;
for (fpga_irq = OMAP1510_IH_FPGA_BASE; for (fpga_irq = OMAP_FPGA_IRQ_BASE;
(fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat; (fpga_irq < OMAP_FPGA_IRQ_END) && stat;
fpga_irq++, stat >>= 1) { fpga_irq++, stat >>= 1) {
if (stat & 1) { if (stat & 1) {
d = irq_desc + fpga_irq; d = irq_desc + fpga_irq;
...@@ -151,7 +151,7 @@ void omap1510_fpga_init_irq(void) ...@@ -151,7 +151,7 @@ void omap1510_fpga_init_irq(void)
__raw_writeb(0, OMAP1510_FPGA_IMR_HI); __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
__raw_writeb(0, INNOVATOR_FPGA_IMR2); __raw_writeb(0, INNOVATOR_FPGA_IMR2);
for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS); i++) { for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) {
if (i == OMAP1510_INT_FPGA_TS) { if (i == OMAP1510_INT_FPGA_TS) {
/* /*
......
arch/arm/mach-omap2/board-sdp-hsmmc.c
View file @ 38c50a71
...@@ -47,7 +47,7 @@ ...@@ -47,7 +47,7 @@
static int sdp_mmc_card_detect(int irq) static int sdp_mmc_card_detect(int irq)
{ {
return twl4030_get_gpio_datain(irq - IH_TWL4030_GPIO_BASE); return twl4030_get_gpio_datain(irq - TWL4030_GPIO_IRQ_BASE);
} }
/* /*
......
drivers/i2c/chips/twl4030-core.c
View file @ 38c50a71
...@@ -486,7 +486,7 @@ static int twl4030_irq_thread(void *data) ...@@ -486,7 +486,7 @@ static int twl4030_irq_thread(void *data)
continue; continue;
} }
for (module_irq = IH_TWL4030_BASE; 0 != pih_isr; for (module_irq = TWL4030_IRQ_BASE; 0 != pih_isr;
pih_isr >>= 1, module_irq++) { pih_isr >>= 1, module_irq++) {
if (pih_isr & 0x1) { if (pih_isr & 0x1) {
irq_desc_t *d = irq_desc + module_irq; irq_desc_t *d = irq_desc + module_irq;
...@@ -874,7 +874,7 @@ static void twl_init_irq(void) ...@@ -874,7 +874,7 @@ static void twl_init_irq(void)
} }
/* install an irq handler for each of the PIH modules */ /* install an irq handler for each of the PIH modules */
for (i = IH_TWL4030_BASE; i < IH_TWL4030_END; i++) { for (i = TWL4030_IRQ_BASE; i < TWL4030_IRQ_END; i++) {
set_irq_chip(i, &twl4030_irq_chip); set_irq_chip(i, &twl4030_irq_chip);
set_irq_handler(i, do_twl4030_module_irq); set_irq_handler(i, do_twl4030_module_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
......
drivers/i2c/chips/twl4030-gpio.c
View file @ 38c50a71
...@@ -243,7 +243,7 @@ static int gpio_write_imr(unsigned int imr) ...@@ -243,7 +243,7 @@ static int gpio_write_imr(unsigned int imr)
*/ */
static void twl4030_gpio_mask_and_ack(unsigned int irq) static void twl4030_gpio_mask_and_ack(unsigned int irq)
{ {
int gpio = irq - IH_TWL4030_GPIO_BASE; int gpio = irq - TWL4030_GPIO_IRQ_BASE;
down(&gpio_sem); down(&gpio_sem);
/* mask */ /* mask */
...@@ -256,7 +256,7 @@ static void twl4030_gpio_mask_and_ack(unsigned int irq) ...@@ -256,7 +256,7 @@ static void twl4030_gpio_mask_and_ack(unsigned int irq)
static void twl4030_gpio_unmask(unsigned int irq) static void twl4030_gpio_unmask(unsigned int irq)
{ {
int gpio = irq - IH_TWL4030_GPIO_BASE; int gpio = irq - TWL4030_GPIO_IRQ_BASE;
down(&gpio_sem); down(&gpio_sem);
gpio_imr_shadow &= ~(1 << gpio); gpio_imr_shadow &= ~(1 << gpio);
...@@ -280,7 +280,7 @@ static void twl4030_gpio_mask_irqchip(unsigned int irq) {} ...@@ -280,7 +280,7 @@ static void twl4030_gpio_mask_irqchip(unsigned int irq) {}
static void twl4030_gpio_unmask_irqchip(unsigned int irq) static void twl4030_gpio_unmask_irqchip(unsigned int irq)
{ {
int gpio = irq - IH_TWL4030_GPIO_BASE; int gpio = irq - TWL4030_GPIO_IRQ_BASE;
gpio_pending_unmask |= (1 << gpio); gpio_pending_unmask |= (1 << gpio);
if (gpio_unmask_thread && gpio_unmask_thread->state != TASK_RUNNING) if (gpio_unmask_thread && gpio_unmask_thread->state != TASK_RUNNING)
...@@ -641,7 +641,7 @@ static int twl4030_gpio_unmask_thread(void *data) ...@@ -641,7 +641,7 @@ static int twl4030_gpio_unmask_thread(void *data)
gpio_pending_unmask = 0; gpio_pending_unmask = 0;
local_irq_enable(); local_irq_enable();
for (irq = IH_TWL4030_GPIO_BASE; 0 != gpio_unmask; for (irq = TWL4030_GPIO_IRQ_BASE; 0 != gpio_unmask;
gpio_unmask >>= 1, irq++) { gpio_unmask >>= 1, irq++) {
if (gpio_unmask & 0x1) if (gpio_unmask & 0x1)
twl4030_gpio_unmask(irq); twl4030_gpio_unmask(irq);
...@@ -733,7 +733,7 @@ static void do_twl4030_gpio_module_irq(unsigned int irq, irq_desc_t *desc) ...@@ -733,7 +733,7 @@ static void do_twl4030_gpio_module_irq(unsigned int irq, irq_desc_t *desc)
gpio_isr = 0; gpio_isr = 0;
up(&gpio_sem); up(&gpio_sem);
for (gpio_irq = IH_TWL4030_GPIO_BASE; 0 != gpio_isr; for (gpio_irq = TWL4030_GPIO_IRQ_BASE; 0 != gpio_isr;
gpio_isr >>= 1, gpio_irq++) { gpio_isr >>= 1, gpio_irq++) {
if (gpio_isr & 0x1) { if (gpio_isr & 0x1) {
irq_desc_t *d = irq_desc + gpio_irq; irq_desc_t *d = irq_desc + gpio_irq;
...@@ -779,7 +779,7 @@ static int __init gpio_twl4030_init(void) ...@@ -779,7 +779,7 @@ static int __init gpio_twl4030_init(void)
if (!ret) { if (!ret) {
/* install an irq handler for each of the gpio interrupts */ /* install an irq handler for each of the gpio interrupts */
for (irq = IH_TWL4030_GPIO_BASE; irq < IH_TWL4030_GPIO_END; for (irq = TWL4030_GPIO_IRQ_BASE; irq < TWL4030_GPIO_IRQ_END;
irq++) { irq++) {
set_irq_chip(irq, &twl4030_gpio_irq_chip); set_irq_chip(irq, &twl4030_gpio_irq_chip);
set_irq_handler(irq, do_twl4030_gpio_irq); set_irq_handler(irq, do_twl4030_gpio_irq);
...@@ -797,8 +797,8 @@ static int __init gpio_twl4030_init(void) ...@@ -797,8 +797,8 @@ static int __init gpio_twl4030_init(void)
} }
printk(KERN_INFO "TWL4030 GPIO Demux: IRQ Range %d to %d," printk(KERN_INFO "TWL4030 GPIO Demux: IRQ Range %d to %d,"
" Initialization %s\n", IH_TWL4030_GPIO_BASE, " Initialization %s\n", TWL4030_GPIO_IRQ_BASE,
IH_TWL4030_GPIO_END, (ret) ? "Failed" : "Success"); TWL4030_GPIO_IRQ_END, (ret) ? "Failed" : "Success");
return ret; return ret;
} }
...@@ -812,7 +812,7 @@ static void __exit gpio_twl4030_exit(void) ...@@ -812,7 +812,7 @@ static void __exit gpio_twl4030_exit(void)
set_irq_flags(TWL4030_MODIRQ_GPIO, 0); set_irq_flags(TWL4030_MODIRQ_GPIO, 0);
/* uninstall the irq handler for each of the gpio interrupts */ /* uninstall the irq handler for each of the gpio interrupts */
for (irq = IH_TWL4030_GPIO_BASE; irq < IH_TWL4030_GPIO_END; irq++) { for (irq = TWL4030_GPIO_IRQ_BASE; irq < TWL4030_GPIO_IRQ_END; irq++) {
set_irq_handler(irq, NULL); set_irq_handler(irq, NULL);
set_irq_flags(irq, 0); set_irq_flags(irq, 0);
} }
......
drivers/i2c/chips/twl4030-pwrirq.c
View file @ 38c50a71
...@@ -44,7 +44,7 @@ static void twl4030_pwrirq_disableint(unsigned int irq) {} ...@@ -44,7 +44,7 @@ static void twl4030_pwrirq_disableint(unsigned int irq) {}
static void twl4030_pwrirq_enableint(unsigned int irq) static void twl4030_pwrirq_enableint(unsigned int irq)
{ {
twl4030_pwrirq_pending_unmask |= 1 << (irq - IH_TWL4030_PWRBASE); twl4030_pwrirq_pending_unmask |= 1 << (irq - TWL4030_PWR_IRQ_BASE);
if (twl4030_pwrirq_unmask_thread && if (twl4030_pwrirq_unmask_thread &&
twl4030_pwrirq_unmask_thread->state != TASK_RUNNING) twl4030_pwrirq_unmask_thread->state != TASK_RUNNING)
wake_up_process(twl4030_pwrirq_unmask_thread); wake_up_process(twl4030_pwrirq_unmask_thread);
...@@ -90,7 +90,7 @@ static void do_twl4030_pwrmodule_irq(unsigned int irq, irq_desc_t *desc) ...@@ -90,7 +90,7 @@ static void do_twl4030_pwrmodule_irq(unsigned int irq, irq_desc_t *desc)
irq); irq);
} else { } else {
local_irq_disable(); local_irq_disable();
twl4030_pwrirq_mask |= 1 << (irq - IH_TWL4030_PWRBASE); twl4030_pwrirq_mask |= 1 << (irq - TWL4030_PWR_IRQ_BASE);
local_irq_enable(); local_irq_enable();
twl4030_i2c_write_u8(TWL4030_MODULE_INT, twl4030_i2c_write_u8(TWL4030_MODULE_INT,
twl4030_pwrirq_mask, PWR_IMR1); twl4030_pwrirq_mask, PWR_IMR1);
...@@ -123,7 +123,7 @@ static void do_twl4030_pwrirq(unsigned int irq, irq_desc_t *desc) ...@@ -123,7 +123,7 @@ static void do_twl4030_pwrirq(unsigned int irq, irq_desc_t *desc)
return; return;
} }
for (module_irq = IH_TWL4030_PWRBASE; pwr_isr != 0; for (module_irq = TWL4030_PWR_IRQ_BASE; pwr_isr != 0;
module_irq++, pwr_isr >>= 1) { module_irq++, pwr_isr >>= 1) {
if (pwr_isr & 1) { if (pwr_isr & 1) {
irq_desc_t *d = irq_desc + module_irq; irq_desc_t *d = irq_desc + module_irq;
...@@ -192,7 +192,7 @@ static int __init twl4030_pwrirq_init(void) ...@@ -192,7 +192,7 @@ static int __init twl4030_pwrirq_init(void)
return -ENOMEM; return -ENOMEM;
} }
for (i = IH_TWL4030_PWRBASE; i < IH_TWL4030_PWRBASE_END; i++) { for (i = TWL4030_PWR_IRQ_BASE; i < TWL4030_PWR_IRQ_END; i++) {
set_irq_chip(i, &twl4030_pwrirq_chip); set_irq_chip(i, &twl4030_pwrirq_chip);
set_irq_handler(i, do_twl4030_pwrmodule_irq); set_irq_handler(i, do_twl4030_pwrmodule_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
...@@ -211,7 +211,7 @@ static void __exit twl4030_pwrirq_exit(void) ...@@ -211,7 +211,7 @@ static void __exit twl4030_pwrirq_exit(void)
set_irq_handler(TWL4030_MODIRQ_PWR, NULL); set_irq_handler(TWL4030_MODIRQ_PWR, NULL);
set_irq_flags(TWL4030_MODIRQ_PWR, 0); set_irq_flags(TWL4030_MODIRQ_PWR, 0);
for (i = IH_TWL4030_PWRBASE; i < IH_TWL4030_PWRBASE_END; i++) { for (i = TWL4030_PWR_IRQ_BASE; i < TWL4030_PWR_IRQ_END; i++) {
set_irq_handler(i, NULL); set_irq_handler(i, NULL);
set_irq_flags(i, 0); set_irq_flags(i, 0);
} }
......
include/asm-arm/arch-omap/board-2430osk.h
View file @ 38c50a71
...@@ -33,26 +33,6 @@ ...@@ -33,26 +33,6 @@
#define OMAP24XX_ETHR_START 0x08000300 #define OMAP24XX_ETHR_START 0x08000300
#define OMAP24XX_ETHR_GPIO_IRQ 149 #define OMAP24XX_ETHR_GPIO_IRQ 149
#ifdef CONFIG_TWL4030_CORE
#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ #define TWL4030_IRQNUM INT_24XX_SYS_NIRQ
/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
#define IH_TWL4030_BASE IH_BOARD_BASE
#define IH_TWL4030_END (IH_TWL4030_BASE+8)
#define IH_TWL4030_PWRBASE (IH_TWL4030_END)
#define IH_TWL4030_PWRBASE_END (IH_TWL4030_PWRBASE+8)
#ifdef CONFIG_TWL4030_GPIO
/* TWL4030 GPIO Interrupts */
#define IH_TWL4030_GPIO_BASE (IH_TWL4030_PWRBASE_END)
#define IH_TWL4030_GPIO_END (IH_TWL4030_GPIO_BASE+18)
#define NR_IRQS (IH_TWL4030_GPIO_END)
#else
#define NR_IRQS (IH_TWL4030_PWRBASE_END)
#endif /* CONFIG_I2C_TWL4030_GPIO */
#endif /* End of support for TWL4030 */
#endif /* __ASM_ARCH_OMAP_2430OSK_H */ #endif /* __ASM_ARCH_OMAP_2430OSK_H */
include/asm-arm/arch-omap/board-2430sdp.h
View file @ 38c50a71
...@@ -34,28 +34,8 @@ ...@@ -34,28 +34,8 @@
#define OMAP24XX_ETHR_GPIO_IRQ 149 #define OMAP24XX_ETHR_GPIO_IRQ 149
#define SDP2430_CS0_BASE 0x04000000 #define SDP2430_CS0_BASE 0x04000000
#ifdef CONFIG_TWL4030_CORE
#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ #define TWL4030_IRQNUM INT_24XX_SYS_NIRQ
/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
#define IH_TWL4030_BASE IH_BOARD_BASE
#define IH_TWL4030_END (IH_TWL4030_BASE+8)
#define IH_TWL4030_PWRBASE (IH_TWL4030_END)
#define IH_TWL4030_PWRBASE_END (IH_TWL4030_PWRBASE+8)
#ifdef CONFIG_TWL4030_GPIO
/* TWL4030 GPIO Interrupts */
#define IH_TWL4030_GPIO_BASE (IH_TWL4030_PWRBASE_END)
#define IH_TWL4030_GPIO_END (IH_TWL4030_GPIO_BASE+18)
#define NR_IRQS (IH_TWL4030_GPIO_END)
#else
#define NR_IRQS (IH_TWL4030_PWRBASE_END)
#endif /* CONFIG_I2C_TWL4030_GPIO */
#endif /* End of support for TWL4030 */
/* Function prototypes */ /* Function prototypes */
extern void sdp2430_flash_init(void); extern void sdp2430_flash_init(void);
extern void sdp2430_usb_init(void); extern void sdp2430_usb_init(void);
......
include/asm-arm/arch-omap/board-3430sdp.h
View file @ 38c50a71
...@@ -67,26 +67,7 @@ extern void sdp_mmc_init(void); ...@@ -67,26 +67,7 @@ extern void sdp_mmc_init(void);
#define FLASH_SIZE_SDPV1 SZ_64M #define FLASH_SIZE_SDPV1 SZ_64M
#define FLASH_SIZE_SDPV2 SZ_128M #define FLASH_SIZE_SDPV2 SZ_128M
#ifdef CONFIG_TWL4030_CORE
#define TWL4030_IRQNUM INT_34XX_SYS_NIRQ #define TWL4030_IRQNUM INT_34XX_SYS_NIRQ
/* TWL4030 Primary Interrupt Handler (PIH) interrupts */ #endif /* __ASM_ARCH_OMAP_3430SDP_H */
#define IH_TWL4030_BASE IH_BOARD_BASE
#define IH_TWL4030_END (IH_TWL4030_BASE+8)
#define IH_TWL4030_PWRBASE (IH_TWL4030_END)
#define IH_TWL4030_PWRBASE_END (IH_TWL4030_PWRBASE+8)
#ifdef CONFIG_TWL4030_GPIO
/* TWL4030 GPIO Interrupts */
#define IH_TWL4030_GPIO_BASE (IH_TWL4030_PWRBASE_END)
#define IH_TWL4030_GPIO_END (IH_TWL4030_GPIO_BASE+18)
#define NR_IRQS (IH_TWL4030_GPIO_END)
#else
#define NR_IRQS (IH_TWL4030_PWRBASE_END)
#endif /* CONFIG_I2C_TWL4030_GPIO */
#endif /* End of support for TWL4030 */
#endif /* __ASM_ARCH_OMAP_3430SDP_H */
include/asm-arm/arch-omap/board-h3.h
View file @ 38c50a71
...@@ -30,12 +30,6 @@ ...@@ -30,12 +30,6 @@
/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
#define OMAP1710_ETHR_START 0x04000300 #define OMAP1710_ETHR_START 0x04000300
#define MAXIRQNUM (IH_BOARD_BASE)
#define MAXFIQNUM MAXIRQNUM
#define MAXSWINUM MAXIRQNUM
#define NR_IRQS (MAXIRQNUM + 1)
extern void h3_mmc_init(void); extern void h3_mmc_init(void);
extern void h3_mmc_slot_cover_handler(void *arg, int state); extern void h3_mmc_slot_cover_handler(void *arg, int state);
......
include/asm-arm/arch-omap/board-innovator.h
View file @ 38c50a71
...@@ -36,9 +36,6 @@ ...@@ -36,9 +36,6 @@
#define OMAP1510P1_EMIFS_PRI_VALUE 0x00 #define OMAP1510P1_EMIFS_PRI_VALUE 0x00
#define OMAP1510P1_EMIFF_PRI_VALUE 0x00 #define OMAP1510P1_EMIFF_PRI_VALUE 0x00
#define NR_FPGA_IRQS 24
#define NR_IRQS (IH_BOARD_BASE + NR_FPGA_IRQS)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
void fpga_write(unsigned char val, int reg); void fpga_write(unsigned char val, int reg);
unsigned char fpga_read(int reg); unsigned char fpga_read(int reg);
......
include/asm-arm/arch-omap/board-omap3beagle.h
View file @ 38c50a71
...@@ -29,25 +29,7 @@ ...@@ -29,25 +29,7 @@
#ifndef __ASM_ARCH_OMAP3_BEAGLE_H #ifndef __ASM_ARCH_OMAP3_BEAGLE_H
#define __ASM_ARCH_OMAP3_BEAGLE_H #define __ASM_ARCH_OMAP3_BEAGLE_H
#ifdef CONFIG_TWL4030_CORE
#define TWL4030_IRQNUM INT_34XX_SYS_NIRQ #define TWL4030_IRQNUM INT_34XX_SYS_NIRQ
/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
#define IH_TWL4030_BASE IH_BOARD_BASE
#define IH_TWL4030_END (IH_TWL4030_BASE+8)
#define IH_TWL4030_PWRBASE (IH_TWL4030_END)
#define IH_TWL4030_PWRBASE_END (IH_TWL4030_PWRBASE+8)
#ifdef CONFIG_TWL4030_GPIO
/* TWL4030 GPIO Interrupts */
#define IH_TWL4030_GPIO_BASE (IH_TWL4030_PWRBASE_END)
#define IH_TWL4030_GPIO_END (IH_TWL4030_GPIO_BASE+18)
#define NR_IRQS (IH_TWL4030_GPIO_END)
#else
#define NR_IRQS (IH_TWL4030_PWRBASE_END)
#endif /* CONFIG_I2C_TWL4030_GPIO */
#endif /* End of support for TWL4030 */
#endif /* __ASM_ARCH_OMAP3_BEAGLE_H */ #endif /* __ASM_ARCH_OMAP3_BEAGLE_H */
include/asm-arm/arch-omap/board-omap3evm.h
View file @ 38c50a71
...@@ -29,25 +29,7 @@ ...@@ -29,25 +29,7 @@
#ifndef __ASM_ARCH_OMAP3_EVM_H #ifndef __ASM_ARCH_OMAP3_EVM_H
#define __ASM_ARCH_OMAP3_EVM_H #define __ASM_ARCH_OMAP3_EVM_H
#ifdef CONFIG_TWL4030_CORE
#define TWL4030_IRQNUM INT_34XX_SYS_NIRQ #define TWL4030_IRQNUM INT_34XX_SYS_NIRQ
/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
#define IH_TWL4030_BASE IH_BOARD_BASE
#define IH_TWL4030_END (IH_TWL4030_BASE+8)
#define IH_TWL4030_PWRBASE (IH_TWL4030_END)
#define IH_TWL4030_PWRBASE_END (IH_TWL4030_PWRBASE+8)
#ifdef CONFIG_TWL4030_GPIO
/* TWL4030 GPIO Interrupts */
#define IH_TWL4030_GPIO_BASE (IH_TWL4030_PWRBASE_END)
#define IH_TWL4030_GPIO_END (IH_TWL4030_GPIO_BASE+18)
#define NR_IRQS (IH_TWL4030_GPIO_END)
#else
#define NR_IRQS (IH_TWL4030_PWRBASE_END)
#endif /* CONFIG_I2C_TWL4030_GPIO */
#endif /* End of support for TWL4030 */
#endif /* __ASM_ARCH_OMAP3_EVM_H */ #endif /* __ASM_ARCH_OMAP3_EVM_H */
include/asm-arm/arch-omap/board-perseus2.h
View file @ 38c50a71
...@@ -36,10 +36,4 @@ ...@@ -36,10 +36,4 @@
#define OMAP_SDRAM_DEVICE D256M_1X16_4B #define OMAP_SDRAM_DEVICE D256M_1X16_4B
#endif #endif
#define MAXIRQNUM IH_BOARD_BASE
#define MAXFIQNUM MAXIRQNUM
#define MAXSWINUM MAXIRQNUM
#define NR_IRQS (MAXIRQNUM + 1)
#endif #endif
include/asm-arm/arch-omap/fpga.h
View file @ 38c50a71
...@@ -169,30 +169,29 @@ struct h2p2_dbg_fpga { ...@@ -169,30 +169,29 @@ struct h2p2_dbg_fpga {
#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) #define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
/* IRQ Numbers for interrupts muxed through the FPGA */ /* IRQ Numbers for interrupts muxed through the FPGA */
#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE #define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0) #define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
#define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1) #define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
#define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2) #define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
#define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3) #define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
#define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4) #define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
#define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5) #define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
#define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6) #define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
#define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7) #define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
#define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8) #define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
#define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9) #define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
#define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10) #define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
#define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11) #define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
#define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12) #define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
#define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13) #define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
#define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14) #define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
#define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15) #define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
#define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16) #define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
#define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17) #define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
#define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18) #define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
#define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19) #define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
#define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20) #define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
#define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21) #define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
#define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22) #define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
#define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23)
#endif #endif
include/asm-arm/arch-omap/irqs.h
View file @ 38c50a71
...@@ -328,7 +328,41 @@ ...@@ -328,7 +328,41 @@
#define OMAP_MAX_GPIO_LINES 192 #define OMAP_MAX_GPIO_LINES 192
#define IH_GPIO_BASE (128 + IH2_BASE) #define IH_GPIO_BASE (128 + IH2_BASE)
#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) #define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
#define IH_BOARD_BASE (16 + IH_MPUIO_BASE) #define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
/* External FPGA handles interrupts on Innovator boards */
#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
#ifdef CONFIG_MACH_OMAP_INNOVATOR
#define OMAP_FPGA_NR_IRQS 24
#else
#define OMAP_FPGA_NR_IRQS 0
#endif
#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
#ifdef CONFIG_TWL4030_CORE
#define TWL4030_BASE_NR_IRQS 8
#define TWL4030_PWR_NR_IRQS 8
#else
#define TWL4030_BASE_NR_IRQS 0
#define TWL4030_PWR_NR_IRQS 0
#endif
#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
/* External TWL4030 gpio interrupts are optional */
#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
#ifdef CONFIG_TWL4030_GPIO
#define TWL4030_GPIO_NR_IRQS 18
#else
#define TWL4030_GPIO_NR_IRQS 0
#endif
#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
/* Total number of interrupts depends on the enabled blocks above */
#define NR_IRQS TWL4030_GPIO_IRQ_END
#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
...@@ -336,14 +370,6 @@ ...@@ -336,14 +370,6 @@
extern void omap_init_irq(void); extern void omap_init_irq(void);
#endif #endif
/*
* The definition of NR_IRQS is in board-specific header file, which is
* included via hardware.h
*/
#include <asm/hardware.h> #include <asm/hardware.h>
#ifndef NR_IRQS
#define NR_IRQS IH_BOARD_BASE
#endif
#endif #endif
include/linux/i2c/twl4030.h
View file @ 38c50a71
...@@ -56,21 +56,21 @@ ...@@ -56,21 +56,21 @@
#include <asm/arch/irqs.h> #include <asm/arch/irqs.h>
/* TWL4030 interrupts */ /* TWL4030 interrupts */
#define TWL4030_MODIRQ_GPIO (IH_TWL4030_BASE + 0) #define TWL4030_MODIRQ_GPIO (TWL4030_IRQ_BASE + 0)
#define TWL4030_MODIRQ_KEYPAD (IH_TWL4030_BASE + 1) #define TWL4030_MODIRQ_KEYPAD (TWL4030_IRQ_BASE + 1)
#define TWL4030_MODIRQ_BCI (IH_TWL4030_BASE + 2) #define TWL4030_MODIRQ_BCI (TWL4030_IRQ_BASE + 2)
#define TWL4030_MODIRQ_MADC (IH_TWL4030_BASE + 3) #define TWL4030_MODIRQ_MADC (TWL4030_IRQ_BASE + 3)
#define TWL4030_MODIRQ_USB (IH_TWL4030_BASE + 4) #define TWL4030_MODIRQ_USB (TWL4030_IRQ_BASE + 4)
#define TWL4030_MODIRQ_PWR (IH_TWL4030_BASE + 5) #define TWL4030_MODIRQ_PWR (TWL4030_IRQ_BASE + 5)
#define TWL4030_PWRIRQ_PWRBTN (IH_TWL4030_PWRBASE + 0) #define TWL4030_PWRIRQ_PWRBTN (TWL4030_PWR_IRQ_BASE + 0)
#define TWL4030_PWRIRQ_CHG_PRES (IH_TWL4030_PWRBASE + 1) #define TWL4030_PWRIRQ_CHG_PRES (TWL4030_PWR_IRQ_BASE + 1)
#define TWL4030_PWRIRQ_USB_PRES (IH_TWL4030_PWRBASE + 2) #define TWL4030_PWRIRQ_USB_PRES (TWL4030_PWR_IRQ_BASE + 2)
#define TWL4030_PWRIRQ_RTC (IH_TWL4030_PWRBASE + 3) #define TWL4030_PWRIRQ_RTC (TWL4030_PWR_IRQ_BASE + 3)
#define TWL4030_PWRIRQ_HOT_DIE (IH_TWL4030_PWRBASE + 4) #define TWL4030_PWRIRQ_HOT_DIE (TWL4030_PWR_IRQ_BASE + 4)
#define TWL4030_PWRIRQ_PWROK_TIMEOUT (IH_TWL4030_PWRBASE + 5) #define TWL4030_PWRIRQ_PWROK_TIMEOUT (TWL4030_PWR_IRQ_BASE + 5)
#define TWL4030_PWRIRQ_MBCHG (IH_TWL4030_PWRBASE + 6) #define TWL4030_PWRIRQ_MBCHG (TWL4030_PWR_IRQ_BASE + 6)
#define TWL4030_PWRIRQ_SC_DETECT (IH_TWL4030_PWRBASE + 7) #define TWL4030_PWRIRQ_SC_DETECT (TWL4030_PWR_IRQ_BASE + 7)
/* Rest are unsued currently*/ /* Rest are unsued currently*/
...@@ -87,7 +87,7 @@ ...@@ -87,7 +87,7 @@
#define TWL4030_GPIO_MIN 0 #define TWL4030_GPIO_MIN 0
#define TWL4030_GPIO_MAX 18 #define TWL4030_GPIO_MAX 18
#define TWL4030_GPIO_MAX_CD 2 #define TWL4030_GPIO_MAX_CD 2
#define TWL4030_GPIO_IRQ_NO(n) (IH_TWL4030_GPIO_BASE+n) #define TWL4030_GPIO_IRQ_NO(n) (TWL4030_GPIO_IRQ_BASE + (n))
#define TWL4030_GPIO_IS_INPUT 1 #define TWL4030_GPIO_IS_INPUT 1
#define TWL4030_GPIO_IS_OUTPUT 0 #define TWL4030_GPIO_IS_OUTPUT 0
#define TWL4030_GPIO_IS_ENABLE 1 #define TWL4030_GPIO_IS_ENABLE 1
......
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