Commit 35d77ef1 authored by Paul Mackerras's avatar Paul Mackerras

Merge branch 'for-2.6.25' of...

Merge branch 'for-2.6.25' of master.kernel.org:/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx into merge
parents 4187377b f62f2fdd
......@@ -17,6 +17,7 @@
#include "44x.h"
#include "cuboot.h"
#define TARGET_4xx
#define TARGET_44x
#include "ppcboot.h"
......
......@@ -17,6 +17,7 @@
#include "44x.h"
#include "cuboot.h"
#define TARGET_4xx
#define TARGET_44x
#include "ppcboot.h"
......
......@@ -22,6 +22,7 @@
#include "44x.h"
#include "cuboot.h"
#define TARGET_4xx
#define TARGET_44x
#include "ppcboot.h"
......
......@@ -21,7 +21,9 @@
#include "dcr.h"
#include "4xx.h"
#define TARGET_4xx
#define TARGET_44x
#define TARGET_440GX
#include "ppcboot.h"
static bd_t bd;
......
......@@ -11,6 +11,7 @@
#include "4xx.h"
#include "cuboot.h"
#define TARGET_4xx
#define TARGET_44x
#include "ppcboot.h"
......
......@@ -235,7 +235,7 @@
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "ibm,plb-pciex-405exr", "ibm,plb-pciex";
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
primary;
port = <0>; /* port number */
reg = <a0000000 20000000 /* Config space access */
......
......@@ -38,8 +38,8 @@
timebase-frequency = <0>; /* Filled in by zImage */
i-cache-line-size = <20>;
d-cache-line-size = <20>;
i-cache-size = <20000>;
d-cache-size = <20000>;
i-cache-size = <8000>;
d-cache-size = <8000>;
dcr-controller;
dcr-access-method = "native";
};
......@@ -136,11 +136,11 @@
};
POB0: opb {
compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
ranges = <00000000 4 e0000000 20000000>;
clock-frequency = <0>; /* Filled in by zImage */
ranges = <00000000 4 e0000000 20000000>;
clock-frequency = <0>; /* Filled in by zImage */
EBC0: ebc {
compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
......@@ -153,38 +153,38 @@
};
UART0: serial@10000200 {
device_type = "serial";
compatible = "ns16550";
reg = <10000200 8>;
device_type = "serial";
compatible = "ns16550";
reg = <10000200 8>;
virtual-reg = <a0000200>;
clock-frequency = <0>; /* Filled in by zImage */
current-speed = <1c200>;
interrupt-parent = <&UIC0>;
interrupts = <0 4>;
};
clock-frequency = <0>; /* Filled in by zImage */
current-speed = <1c200>;
interrupt-parent = <&UIC0>;
interrupts = <0 4>;
};
UART1: serial@10000300 {
device_type = "serial";
compatible = "ns16550";
reg = <10000300 8>;
device_type = "serial";
compatible = "ns16550";
reg = <10000300 8>;
virtual-reg = <a0000300>;
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <1 4>;
};
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC0>;
interrupts = <1 4>;
};
UART2: serial@10000600 {
device_type = "serial";
compatible = "ns16550";
reg = <10000600 8>;
device_type = "serial";
compatible = "ns16550";
reg = <10000600 8>;
virtual-reg = <a0000600>;
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC1>;
interrupts = <5 4>;
};
clock-frequency = <0>;
current-speed = <0>;
interrupt-parent = <&UIC1>;
interrupts = <5 4>;
};
IIC0: i2c@10000400 {
compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
......
......@@ -73,8 +73,8 @@
#define XHI_BUFFER_START 0
/**
* buffer_icap_get_status: Get the contents of the status register.
* @parameter base_address: is the base address of the device
* buffer_icap_get_status - Get the contents of the status register.
* @base_address: is the base address of the device
*
* The status register contains the ICAP status and the done bit.
*
......@@ -94,9 +94,9 @@ static inline u32 buffer_icap_get_status(void __iomem *base_address)
}
/**
* buffer_icap_get_bram: Reads data from the storage buffer bram.
* @parameter base_address: contains the base address of the component.
* @parameter offset: The word offset from which the data should be read.
* buffer_icap_get_bram - Reads data from the storage buffer bram.
* @base_address: contains the base address of the component.
* @offset: The word offset from which the data should be read.
*
* A bram is used as a configuration memory cache. One frame of data can
* be stored in this "storage buffer".
......@@ -108,8 +108,8 @@ static inline u32 buffer_icap_get_bram(void __iomem *base_address,
}
/**
* buffer_icap_busy: Return true if the icap device is busy
* @parameter base_address: is the base address of the device
* buffer_icap_busy - Return true if the icap device is busy
* @base_address: is the base address of the device
*
* The queries the low order bit of the status register, which
* indicates whether the current configuration or readback operation
......@@ -121,8 +121,8 @@ static inline bool buffer_icap_busy(void __iomem *base_address)
}
/**
* buffer_icap_busy: Return true if the icap device is not busy
* @parameter base_address: is the base address of the device
* buffer_icap_busy - Return true if the icap device is not busy
* @base_address: is the base address of the device
*
* The queries the low order bit of the status register, which
* indicates whether the current configuration or readback operation
......@@ -134,9 +134,9 @@ static inline bool buffer_icap_done(void __iomem *base_address)
}
/**
* buffer_icap_set_size: Set the size register.
* @parameter base_address: is the base address of the device
* @parameter data: The size in bytes.
* buffer_icap_set_size - Set the size register.
* @base_address: is the base address of the device
* @data: The size in bytes.
*
* The size register holds the number of 8 bit bytes to transfer between
* bram and the icap (or icap to bram).
......@@ -148,9 +148,9 @@ static inline void buffer_icap_set_size(void __iomem *base_address,
}
/**
* buffer_icap_mSetoffsetReg: Set the bram offset register.
* @parameter base_address: contains the base address of the device.
* @parameter data: is the value to be written to the data register.
* buffer_icap_set_offset - Set the bram offset register.
* @base_address: contains the base address of the device.
* @data: is the value to be written to the data register.
*
* The bram offset register holds the starting bram address to transfer
* data from during configuration or write data to during readback.
......@@ -162,9 +162,9 @@ static inline void buffer_icap_set_offset(void __iomem *base_address,
}
/**
* buffer_icap_set_rnc: Set the RNC (Readback not Configure) register.
* @parameter base_address: contains the base address of the device.
* @parameter data: is the value to be written to the data register.
* buffer_icap_set_rnc - Set the RNC (Readback not Configure) register.
* @base_address: contains the base address of the device.
* @data: is the value to be written to the data register.
*
* The RNC register determines the direction of the data transfer. It
* controls whether a configuration or readback take place. Writing to
......@@ -178,10 +178,10 @@ static inline void buffer_icap_set_rnc(void __iomem *base_address,
}
/**
* buffer_icap_set_bram: Write data to the storage buffer bram.
* @parameter base_address: contains the base address of the component.
* @parameter offset: The word offset at which the data should be written.
* @parameter data: The value to be written to the bram offset.
* buffer_icap_set_bram - Write data to the storage buffer bram.
* @base_address: contains the base address of the component.
* @offset: The word offset at which the data should be written.
* @data: The value to be written to the bram offset.
*
* A bram is used as a configuration memory cache. One frame of data can
* be stored in this "storage buffer".
......@@ -193,10 +193,10 @@ static inline void buffer_icap_set_bram(void __iomem *base_address,
}
/**
* buffer_icap_device_read: Transfer bytes from ICAP to the storage buffer.
* @parameter drvdata: a pointer to the drvdata.
* @parameter offset: The storage buffer start address.
* @parameter count: The number of words (32 bit) to read from the
* buffer_icap_device_read - Transfer bytes from ICAP to the storage buffer.
* @drvdata: a pointer to the drvdata.
* @offset: The storage buffer start address.
* @count: The number of words (32 bit) to read from the
* device (ICAP).
**/
static int buffer_icap_device_read(struct hwicap_drvdata *drvdata,
......@@ -227,10 +227,10 @@ static int buffer_icap_device_read(struct hwicap_drvdata *drvdata,
};
/**
* buffer_icap_device_write: Transfer bytes from ICAP to the storage buffer.
* @parameter drvdata: a pointer to the drvdata.
* @parameter offset: The storage buffer start address.
* @parameter count: The number of words (32 bit) to read from the
* buffer_icap_device_write - Transfer bytes from ICAP to the storage buffer.
* @drvdata: a pointer to the drvdata.
* @offset: The storage buffer start address.
* @count: The number of words (32 bit) to read from the
* device (ICAP).
**/
static int buffer_icap_device_write(struct hwicap_drvdata *drvdata,
......@@ -261,8 +261,8 @@ static int buffer_icap_device_write(struct hwicap_drvdata *drvdata,
};
/**
* buffer_icap_reset: Reset the logic of the icap device.
* @parameter drvdata: a pointer to the drvdata.
* buffer_icap_reset - Reset the logic of the icap device.
* @drvdata: a pointer to the drvdata.
*
* Writing to the status register resets the ICAP logic in an internal
* version of the core. For the version of the core published in EDK,
......@@ -274,10 +274,10 @@ void buffer_icap_reset(struct hwicap_drvdata *drvdata)
}
/**
* buffer_icap_set_configuration: Load a partial bitstream from system memory.
* @parameter drvdata: a pointer to the drvdata.
* @parameter data: Kernel address of the partial bitstream.
* @parameter size: the size of the partial bitstream in 32 bit words.
* buffer_icap_set_configuration - Load a partial bitstream from system memory.
* @drvdata: a pointer to the drvdata.
* @data: Kernel address of the partial bitstream.
* @size: the size of the partial bitstream in 32 bit words.
**/
int buffer_icap_set_configuration(struct hwicap_drvdata *drvdata, u32 *data,
u32 size)
......@@ -333,10 +333,10 @@ int buffer_icap_set_configuration(struct hwicap_drvdata *drvdata, u32 *data,
};
/**
* buffer_icap_get_configuration: Read configuration data from the device.
* @parameter drvdata: a pointer to the drvdata.
* @parameter data: Address of the data representing the partial bitstream
* @parameter size: the size of the partial bitstream in 32 bit words.
* buffer_icap_get_configuration - Read configuration data from the device.
* @drvdata: a pointer to the drvdata.
* @data: Address of the data representing the partial bitstream
* @size: the size of the partial bitstream in 32 bit words.
**/
int buffer_icap_get_configuration(struct hwicap_drvdata *drvdata, u32 *data,
u32 size)
......
......@@ -94,9 +94,9 @@
/**
* fifo_icap_fifo_write: Write data to the write FIFO.
* @parameter drvdata: a pointer to the drvdata.
* @parameter data: the 32-bit value to be written to the FIFO.
* fifo_icap_fifo_write - Write data to the write FIFO.
* @drvdata: a pointer to the drvdata.
* @data: the 32-bit value to be written to the FIFO.
*
* This function will silently fail if the fifo is full.
**/
......@@ -108,8 +108,8 @@ static inline void fifo_icap_fifo_write(struct hwicap_drvdata *drvdata,
}
/**
* fifo_icap_fifo_read: Read data from the Read FIFO.
* @parameter drvdata: a pointer to the drvdata.
* fifo_icap_fifo_read - Read data from the Read FIFO.
* @drvdata: a pointer to the drvdata.
*
* This function will silently fail if the fifo is empty.
**/
......@@ -121,9 +121,9 @@ static inline u32 fifo_icap_fifo_read(struct hwicap_drvdata *drvdata)
}
/**
* fifo_icap_set_read_size: Set the the size register.
* @parameter drvdata: a pointer to the drvdata.
* @parameter data: the size of the following read transaction, in words.
* fifo_icap_set_read_size - Set the the size register.
* @drvdata: a pointer to the drvdata.
* @data: the size of the following read transaction, in words.
**/
static inline void fifo_icap_set_read_size(struct hwicap_drvdata *drvdata,
u32 data)
......@@ -132,8 +132,8 @@ static inline void fifo_icap_set_read_size(struct hwicap_drvdata *drvdata,
}
/**
* fifo_icap_start_config: Initiate a configuration (write) to the device.
* @parameter drvdata: a pointer to the drvdata.
* fifo_icap_start_config - Initiate a configuration (write) to the device.
* @drvdata: a pointer to the drvdata.
**/
static inline void fifo_icap_start_config(struct hwicap_drvdata *drvdata)
{
......@@ -142,8 +142,8 @@ static inline void fifo_icap_start_config(struct hwicap_drvdata *drvdata)
}
/**
* fifo_icap_start_readback: Initiate a readback from the device.
* @parameter drvdata: a pointer to the drvdata.
* fifo_icap_start_readback - Initiate a readback from the device.
* @drvdata: a pointer to the drvdata.
**/
static inline void fifo_icap_start_readback(struct hwicap_drvdata *drvdata)
{
......@@ -152,8 +152,8 @@ static inline void fifo_icap_start_readback(struct hwicap_drvdata *drvdata)
}
/**
* fifo_icap_busy: Return true if the ICAP is still processing a transaction.
* @parameter drvdata: a pointer to the drvdata.
* fifo_icap_busy - Return true if the ICAP is still processing a transaction.
* @drvdata: a pointer to the drvdata.
**/
static inline u32 fifo_icap_busy(struct hwicap_drvdata *drvdata)
{
......@@ -163,8 +163,8 @@ static inline u32 fifo_icap_busy(struct hwicap_drvdata *drvdata)
}
/**
* fifo_icap_write_fifo_vacancy: Query the write fifo available space.
* @parameter drvdata: a pointer to the drvdata.
* fifo_icap_write_fifo_vacancy - Query the write fifo available space.
* @drvdata: a pointer to the drvdata.
*
* Return the number of words that can be safely pushed into the write fifo.
**/
......@@ -175,8 +175,8 @@ static inline u32 fifo_icap_write_fifo_vacancy(
}
/**
* fifo_icap_read_fifo_occupancy: Query the read fifo available data.
* @parameter drvdata: a pointer to the drvdata.
* fifo_icap_read_fifo_occupancy - Query the read fifo available data.
* @drvdata: a pointer to the drvdata.
*
* Return the number of words that can be safely read from the read fifo.
**/
......@@ -187,11 +187,11 @@ static inline u32 fifo_icap_read_fifo_occupancy(
}
/**
* fifo_icap_set_configuration: Send configuration data to the ICAP.
* @parameter drvdata: a pointer to the drvdata.
* @parameter frame_buffer: a pointer to the data to be written to the
* fifo_icap_set_configuration - Send configuration data to the ICAP.
* @drvdata: a pointer to the drvdata.
* @frame_buffer: a pointer to the data to be written to the
* ICAP device.
* @parameter num_words: the number of words (32 bit) to write to the ICAP
* @num_words: the number of words (32 bit) to write to the ICAP
* device.
* This function writes the given user data to the Write FIFO in
......@@ -266,10 +266,10 @@ int fifo_icap_set_configuration(struct hwicap_drvdata *drvdata,
}
/**
* fifo_icap_get_configuration: Read configuration data from the device.
* @parameter drvdata: a pointer to the drvdata.
* @parameter data: Address of the data representing the partial bitstream
* @parameter size: the size of the partial bitstream in 32 bit words.
* fifo_icap_get_configuration - Read configuration data from the device.
* @drvdata: a pointer to the drvdata.
* @data: Address of the data representing the partial bitstream
* @size: the size of the partial bitstream in 32 bit words.
*
* This function reads the specified number of words from the ICAP device in
* the polled mode.
......@@ -335,8 +335,8 @@ int fifo_icap_get_configuration(struct hwicap_drvdata *drvdata,
}
/**
* buffer_icap_reset: Reset the logic of the icap device.
* @parameter drvdata: a pointer to the drvdata.
* buffer_icap_reset - Reset the logic of the icap device.
* @drvdata: a pointer to the drvdata.
*
* This function forces the software reset of the complete HWICAP device.
* All the registers will return to the default value and the FIFO is also
......@@ -360,8 +360,8 @@ void fifo_icap_reset(struct hwicap_drvdata *drvdata)
}
/**
* fifo_icap_flush_fifo: This function flushes the FIFOs in the device.
* @parameter drvdata: a pointer to the drvdata.
* fifo_icap_flush_fifo - This function flushes the FIFOs in the device.
* @drvdata: a pointer to the drvdata.
*/
void fifo_icap_flush_fifo(struct hwicap_drvdata *drvdata)
{
......
This diff is collapsed.
......@@ -48,9 +48,9 @@ struct hwicap_drvdata {
u8 write_buffer[4];
u32 read_buffer_in_use; /* Always in [0,3] */
u8 read_buffer[4];
u32 mem_start; /* phys. address of the control registers */
u32 mem_end; /* phys. address of the control registers */
u32 mem_size;
resource_size_t mem_start;/* phys. address of the control registers */
resource_size_t mem_end; /* phys. address of the control registers */
resource_size_t mem_size;
void __iomem *base_address;/* virt. address of the control registers */
struct device *dev;
......@@ -61,7 +61,7 @@ struct hwicap_drvdata {
const struct config_registers *config_regs;
void *private_data;
bool is_open;
struct semaphore sem;
struct mutex sem;
};
struct hwicap_driver_config {
......@@ -164,29 +164,29 @@ struct config_registers {
#define XHI_DISABLED_AUTO_CRC 0x0000DEFCUL
/**
* hwicap_type_1_read: Generates a Type 1 read packet header.
* @parameter: Register is the address of the register to be read back.
* hwicap_type_1_read - Generates a Type 1 read packet header.
* @reg: is the address of the register to be read back.
*
* Generates a Type 1 read packet header, which is used to indirectly
* read registers in the configuration logic. This packet must then
* be sent through the icap device, and a return packet received with
* the information.
**/
static inline u32 hwicap_type_1_read(u32 Register)
static inline u32 hwicap_type_1_read(u32 reg)
{
return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
(Register << XHI_REGISTER_SHIFT) |
(reg << XHI_REGISTER_SHIFT) |
(XHI_OP_READ << XHI_OP_SHIFT);
}
/**
* hwicap_type_1_write: Generates a Type 1 write packet header
* @parameter: Register is the address of the register to be read back.
* hwicap_type_1_write - Generates a Type 1 write packet header
* @reg: is the address of the register to be read back.
**/
static inline u32 hwicap_type_1_write(u32 Register)
static inline u32 hwicap_type_1_write(u32 reg)
{
return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
(Register << XHI_REGISTER_SHIFT) |
(reg << XHI_REGISTER_SHIFT) |
(XHI_OP_WRITE << XHI_OP_SHIFT);
}
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment