Commit 33c99075 authored by Juha Yrjola's avatar Juha Yrjola Committed by Tony Lindgren

ARM: OMAP2: Place SMS and SDRC into smart idle mode

Place SMS and SDRC into smart idle mode
Signed-off-by: default avatarJuha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 81cfe79b
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
extern void omap_sram_init(void); extern void omap_sram_init(void);
extern int omap2_clk_init(void); extern int omap2_clk_init(void);
extern void omap2_check_revision(void); extern void omap2_check_revision(void);
extern void omap2_init_memory(void);
extern void gpmc_init(void); extern void gpmc_init(void);
extern void omapfb_reserve_sdram(void); extern void omapfb_reserve_sdram(void);
...@@ -80,5 +81,6 @@ void __init omap2_init_common_hw(void) ...@@ -80,5 +81,6 @@ void __init omap2_init_common_hw(void)
{ {
omap2_mux_init(); omap2_mux_init();
omap2_clk_init(); omap2_clk_init();
omap2_init_memory();
gpmc_init(); gpmc_init();
} }
...@@ -30,6 +30,38 @@ ...@@ -30,6 +30,38 @@
#include "prcm-regs.h" #include "prcm-regs.h"
#include "memory.h" #include "memory.h"
#define SMS_BASE 0x68008000
#define SMS_SYSCONFIG 0x010
#define SDRC_BASE 0x68009000
#define SDRC_SYSCONFIG 0x010
#define SDRC_SYSSTATUS 0x014
static const u32 sms_base = IO_ADDRESS(SMS_BASE);
static const u32 sdrc_base = IO_ADDRESS(SDRC_BASE);
static inline void sms_write_reg(int idx, u32 val)
{
__raw_writel(val, sms_base + idx);
}
static inline u32 sms_read_reg(int idx)
{
return __raw_readl(sms_base + idx);
}
static inline void sdrc_write_reg(int idx, u32 val)
{
__raw_writel(val, sdrc_base + idx);
}
static inline u32 sdrc_read_reg(int idx)
{
return __raw_readl(sdrc_base + idx);
}
static struct memory_timings mem_timings; static struct memory_timings mem_timings;
u32 omap2_memory_get_slow_dll_ctrl(void) u32 omap2_memory_get_slow_dll_ctrl(void)
...@@ -99,3 +131,19 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) ...@@ -99,3 +131,19 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
/* 90 degree phase for anything below 133Mhz + disable DLL filter */ /* 90 degree phase for anything below 133Mhz + disable DLL filter */
mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
} }
void __init omap2_init_memory(void)
{
u32 l;
l = sms_read_reg(SMS_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
sms_write_reg(SMS_SYSCONFIG, l);
l = sdrc_read_reg(SDRC_SYSCONFIG);
l &= ~(0x3 << 3);
l |= (0x2 << 3);
sdrc_write_reg(SDRC_SYSCONFIG, l);
}
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