Commit 28f9f19d authored by Russell King's avatar Russell King

Merge branch 'devel' of...

Merge branch 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel
parents 40262b2b 52a7a1ce
......@@ -738,18 +738,22 @@ M: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
M: Dirk Opfer <dirk@opfer-online.de>
S: Maintained
ARM/PALMTX,PALMT5,PALMLD,PALMTE2 SUPPORT
M: Marek Vasut <marek.vasut@gmail.com>
ARM/PALMTX,PALMT5,PALMLD,PALMTE2,PALMTC SUPPORT
P: Marek Vasut
M: marek.vasut@gmail.com
L: linux-arm-kernel@lists.infradead.org
W: http://hackndev.com
S: Maintained
ARM/PALM TREO 680 SUPPORT
M: Tomas Cech <sleep_walker@suse.cz>
L: linux-arm-kernel@lists.infradead.org
W: http://hackndev.com
S: Maintained
ARM/PALMZ72 SUPPORT
M: Sergey Lapin <slapin@ossfans.org>
L: linux-arm-kernel@lists.infradead.org
W: http://hackndev.com
S: Maintained
......
......@@ -78,7 +78,10 @@ static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
#else
static inline int cpu_is_xsc3(void)
{
if ((read_cpuid_id() & 0xffffe000) == 0x69056000)
unsigned int id;
id = read_cpuid_id() & 0xffffe000;
/* It covers both Intel ID and Marvell ID */
if ((id == 0x69056000) || (id == 0x56056000))
return 1;
return 0;
......
......@@ -21,6 +21,11 @@ config CPU_PXA930
config CPU_PXA935
bool "PXA935 (codename Tavor-P65)"
select CPU_PXA930
config CPU_PXA950
bool "PXA950 (codename Tavor-PV2)"
select CPU_PXA930
endmenu
......@@ -79,6 +84,12 @@ config MACH_MP900C
bool "Nec Mobilepro 900/c"
select PXA25x
config MACH_BALLOON3
bool "Balloon 3 board"
select PXA27x
select IWMMXT
select PXA_HAVE_BOARD_IRQS
config ARCH_PXA_IDP
bool "Accelent Xscale IDP"
select PXA25x
......@@ -371,6 +382,15 @@ config MACH_PALMTE2
Say Y here if you intend to run this kernel on a Palm Tungsten|E2
handheld computer.
config MACH_PALMTC
bool "Palm Tungsten|C"
default y
depends on ARCH_PXA_PALM
select PXA25x
help
Say Y here if you intend to run this kernel on a Palm Tungsten|C
handheld computer.
config MACH_PALMT5
bool "Palm Tungsten|T5"
default y
......@@ -458,6 +478,7 @@ config PXA_EZX
select PXA27x
select IWMMXT
select HAVE_PWM
select PXA_HAVE_BOARD_IRQS
config MACH_EZX_A780
bool "Motorola EZX A780"
......@@ -489,6 +510,21 @@ config MACH_EZX_E2
default y
depends on PXA_EZX
config MACH_XCEP
bool "Iskratel Electronics XCEP"
select PXA25x
select MTD
select MTD_PARTITIONS
select MTD_PHYSMAP
select MTD_CFI_INTELEXT
select MTD_CFI
select MTD_CHAR
select SMC91X
select PXA_SSP
help
PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash.
Tuned for usage in Libera instruments for particle accelerators.
endmenu
config PXA25x
......
......@@ -31,6 +31,7 @@ obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o
obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
obj-$(CONFIG_MACH_BALLOON3) += balloon3.o
obj-$(CONFIG_MACH_MP900C) += mp900.o
obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
......@@ -58,6 +59,7 @@ obj-$(CONFIG_MACH_E750) += e750.o
obj-$(CONFIG_MACH_E400) += e400.o
obj-$(CONFIG_MACH_E800) += e800.o
obj-$(CONFIG_MACH_PALMTE2) += palmte2.o
obj-$(CONFIG_MACH_PALMTC) += palmtc.o
obj-$(CONFIG_MACH_PALMT5) += palmt5.o
obj-$(CONFIG_MACH_PALMTX) += palmtx.o
obj-$(CONFIG_MACH_PALMLD) += palmld.o
......@@ -78,6 +80,8 @@ obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx.o cm-x255.o cm-x270.o
obj-$(CONFIG_MACH_CM_X300) += cm-x300.o
obj-$(CONFIG_PXA_EZX) += ezx.o
obj-$(CONFIG_MACH_XCEP) += xcep.o
obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o
obj-$(CONFIG_MACH_STARGATE2) += stargate2.o
obj-$(CONFIG_MACH_CSB726) += csb726.o
......
/*
* linux/arch/arm/mach-pxa/balloon3.c
*
* Support for Balloonboard.org Balloon3 board.
*
* Author: Nick Bane, Wookey, Jonathan McDowell
* Created: June, 2006
* Copyright: Toby Churchill Ltd
* Derived from mainstone.c, by Nico Pitre
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/bitops.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/types.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/sizes.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>
#include <mach/pxa27x.h>
#include <mach/balloon3.h>
#include <mach/audio.h>
#include <mach/pxafb.h>
#include <mach/mmc.h>
#include <mach/udc.h>
#include <mach/pxa27x-udc.h>
#include <mach/irda.h>
#include <mach/ohci.h>
#include <plat/i2c.h>
#include "generic.h"
#include "devices.h"
static unsigned long balloon3_irq_enabled;
static unsigned long balloon3_features_present =
(1 << BALLOON3_FEATURE_OHCI) | (1 << BALLOON3_FEATURE_CF) |
(1 << BALLOON3_FEATURE_AUDIO) |
(1 << BALLOON3_FEATURE_TOPPOLY);
int balloon3_has(enum balloon3_features feature)
{
return (balloon3_features_present & (1 << feature)) ? 1 : 0;
}
EXPORT_SYMBOL_GPL(balloon3_has);
int __init parse_balloon3_features(char *arg)
{
if (!arg)
return 0;
return strict_strtoul(arg, 0, &balloon3_features_present);
}
early_param("balloon3_features", parse_balloon3_features);
static void balloon3_mask_irq(unsigned int irq)
{
int balloon3_irq = (irq - BALLOON3_IRQ(0));
balloon3_irq_enabled &= ~(1 << balloon3_irq);
__raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG);
}
static void balloon3_unmask_irq(unsigned int irq)
{
int balloon3_irq = (irq - BALLOON3_IRQ(0));
balloon3_irq_enabled |= (1 << balloon3_irq);
__raw_writel(~balloon3_irq_enabled, BALLOON3_INT_CONTROL_REG);
}
static struct irq_chip balloon3_irq_chip = {
.name = "FPGA",
.ack = balloon3_mask_irq,
.mask = balloon3_mask_irq,
.unmask = balloon3_unmask_irq,
};
static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned long pending = __raw_readl(BALLOON3_INT_CONTROL_REG) &
balloon3_irq_enabled;
do {
/* clear useless edge notification */
if (desc->chip->ack)
desc->chip->ack(BALLOON3_AUX_NIRQ);
while (pending) {
irq = BALLOON3_IRQ(0) + __ffs(pending);
generic_handle_irq(irq);
pending &= pending - 1;
}
pending = __raw_readl(BALLOON3_INT_CONTROL_REG) &
balloon3_irq_enabled;
} while (pending);
}
static void __init balloon3_init_irq(void)
{
int irq;
pxa27x_init_irq();
/* setup extra Balloon3 irqs */
for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
set_irq_chip(irq, &balloon3_irq_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING);
pr_debug("%s: chained handler installed - irq %d automatically "
"enabled\n", __func__, BALLOON3_AUX_NIRQ);
}
static void balloon3_backlight_power(int on)
{
pr_debug("%s: power is %s\n", __func__, on ? "on" : "off");
gpio_set_value(BALLOON3_GPIO_RUN_BACKLIGHT, on);
}
static unsigned long balloon3_lcd_pin_config[] = {
/* LCD - 16bpp Active TFT */
GPIO58_LCD_LDD_0,
GPIO59_LCD_LDD_1,
GPIO60_LCD_LDD_2,
GPIO61_LCD_LDD_3,
GPIO62_LCD_LDD_4,
GPIO63_LCD_LDD_5,
GPIO64_LCD_LDD_6,
GPIO65_LCD_LDD_7,
GPIO66_LCD_LDD_8,
GPIO67_LCD_LDD_9,
GPIO68_LCD_LDD_10,
GPIO69_LCD_LDD_11,
GPIO70_LCD_LDD_12,
GPIO71_LCD_LDD_13,
GPIO72_LCD_LDD_14,
GPIO73_LCD_LDD_15,
GPIO74_LCD_FCLK,
GPIO75_LCD_LCLK,
GPIO76_LCD_PCLK,
GPIO77_LCD_BIAS,
GPIO99_GPIO, /* Backlight */
};
static struct pxafb_mode_info balloon3_lcd_modes[] = {
{
.pixclock = 38000,
.xres = 480,
.yres = 640,
.bpp = 16,
.hsync_len = 8,
.left_margin = 8,
.right_margin = 8,
.vsync_len = 2,
.upper_margin = 4,
.lower_margin = 5,
.sync = 0,
},
};
static struct pxafb_mach_info balloon3_pxafb_info = {
.modes = balloon3_lcd_modes,
.num_modes = ARRAY_SIZE(balloon3_lcd_modes),
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
.pxafb_backlight_power = balloon3_backlight_power,
};
static unsigned long balloon3_mmc_pin_config[] = {
GPIO32_MMC_CLK,
GPIO92_MMC_DAT_0,
GPIO109_MMC_DAT_1,
GPIO110_MMC_DAT_2,
GPIO111_MMC_DAT_3,
GPIO112_MMC_CMD,
};
static void balloon3_mci_setpower(struct device *dev, unsigned int vdd)
{
struct pxamci_platform_data *p_d = dev->platform_data;
if ((1 << vdd) & p_d->ocr_mask) {
pr_debug("%s: on\n", __func__);
/* FIXME something to prod here? */
} else {
pr_debug("%s: off\n", __func__);
/* FIXME something to prod here? */
}
}
static struct pxamci_platform_data balloon3_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.setpower = balloon3_mci_setpower,
};
static int balloon3_udc_is_connected(void)
{
pr_debug("%s: udc connected\n", __func__);
return 1;
}
static void balloon3_udc_command(int cmd)
{
switch (cmd) {
case PXA2XX_UDC_CMD_CONNECT:
UP2OCR |= (UP2OCR_DPPUE + UP2OCR_DPPUBE);
pr_debug("%s: connect\n", __func__);
break;
case PXA2XX_UDC_CMD_DISCONNECT:
UP2OCR &= ~UP2OCR_DPPUE;
pr_debug("%s: disconnect\n", __func__);
break;
}
}
static struct pxa2xx_udc_mach_info balloon3_udc_info = {
.udc_is_connected = balloon3_udc_is_connected,
.udc_command = balloon3_udc_command,
};
static struct pxaficp_platform_data balloon3_ficp_platform_data = {
.transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
};
static unsigned long balloon3_ohci_pin_config[] = {
GPIO88_USBH1_PWR,
GPIO89_USBH1_PEN,
};
static struct pxaohci_platform_data balloon3_ohci_platform_data = {
.port_mode = PMM_PERPORT_MODE,
.flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
};
static unsigned long balloon3_pin_config[] __initdata = {
/* Select BTUART 'COM1/ttyS0' as IO option for pins 42/43/44/45 */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO44_BTUART_CTS,
GPIO45_BTUART_RTS,
/* Wakeup GPIO */
GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
/* NAND & IDLE LED GPIOs */
GPIO9_GPIO,
GPIO10_GPIO,
};
static struct gpio_led balloon3_gpio_leds[] = {
{
.name = "balloon3:green:idle",
.default_trigger = "heartbeat",
.gpio = BALLOON3_GPIO_LED_IDLE,
.active_low = 1,
},
{
.name = "balloon3:green:nand",
.default_trigger = "nand-disk",
.gpio = BALLOON3_GPIO_LED_NAND,
.active_low = 1,
},
};
static struct gpio_led_platform_data balloon3_gpio_leds_platform_data = {
.leds = balloon3_gpio_leds,
.num_leds = ARRAY_SIZE(balloon3_gpio_leds),
};
static struct platform_device balloon3led_device = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &balloon3_gpio_leds_platform_data,
},
};
static void __init balloon3_init(void)
{
pr_info("Initialising Balloon3\n");
/* system bus arbiter setting
* - Core_Park
* - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
*/
ARB_CNTRL = ARB_CORE_PARK | 0x234;
pxa_set_i2c_info(NULL);
if (balloon3_has(BALLOON3_FEATURE_AUDIO))
pxa_set_ac97_info(NULL);
if (balloon3_has(BALLOON3_FEATURE_TOPPOLY)) {
pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_lcd_pin_config));
gpio_request(BALLOON3_GPIO_RUN_BACKLIGHT,
"LCD Backlight Power");
gpio_direction_output(BALLOON3_GPIO_RUN_BACKLIGHT, 1);
set_pxa_fb_info(&balloon3_pxafb_info);
}
if (balloon3_has(BALLOON3_FEATURE_MMC)) {
pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_mmc_pin_config));
pxa_set_mci_info(&balloon3_mci_platform_data);
}
pxa_set_ficp_info(&balloon3_ficp_platform_data);
if (balloon3_has(BALLOON3_FEATURE_OHCI)) {
pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_ohci_pin_config));
pxa_set_ohci_info(&balloon3_ohci_platform_data);
}
pxa_set_udc_info(&balloon3_udc_info);
pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_pin_config));
platform_device_register(&balloon3led_device);
}
static struct map_desc balloon3_io_desc[] __initdata = {
{ /* CPLD/FPGA */
.virtual = BALLOON3_FPGA_VIRT,
.pfn = __phys_to_pfn(BALLOON3_FPGA_PHYS),
.length = BALLOON3_FPGA_LENGTH,
.type = MT_DEVICE,
},
};
static void __init balloon3_map_io(void)
{
pxa_map_io();
iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc));
}
MACHINE_START(BALLOON3, "Balloon3")
/* Maintainer: Nick Bane. */
.phys_io = 0x40000000,
.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
.map_io = balloon3_map_io,
.init_irq = balloon3_init_irq,
.timer = &pxa_timer,
.init_machine = balloon3_init,
.boot_params = PHYS_OFFSET + 0x100,
MACHINE_END
......@@ -12,7 +12,6 @@ struct clk {
unsigned int cken;
unsigned int delay;
unsigned int enabled;
struct clk *other;
};
#define INIT_CLKREG(_clk,_devname,_conname) \
......
......@@ -13,13 +13,18 @@
#include <linux/sysdev.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/rtc-v3020.h>
#include <video/mbxfb.h>
#include <linux/spi/spi.h>
#include <linux/spi/libertas_spi.h>
#include <mach/pxa27x.h>
#include <mach/ohci.h>
#include <mach/mmc.h>
#include <mach/pxa2xx_spi.h>
#include "generic.h"
......@@ -34,6 +39,10 @@
/* MMC power enable */
#define GPIO105_MMC_POWER (105)
/* WLAN GPIOS */
#define GPIO19_WLAN_STRAP (19)
#define GPIO102_WLAN_RST (102)
static unsigned long cmx270_pin_config[] = {
/* AC'97 */
GPIO28_AC97_BITCLK,
......@@ -94,8 +103,8 @@ static unsigned long cmx270_pin_config[] = {
GPIO26_SSP1_RXD,
/* SSP2 */
GPIO19_SSP2_SCLK,
GPIO14_SSP2_SFRM,
GPIO19_GPIO, /* SSP2 clock is used as GPIO for Libertas pin-strap */
GPIO14_GPIO,
GPIO87_SSP2_TXD,
GPIO88_SSP2_RXD,
......@@ -123,6 +132,7 @@ static unsigned long cmx270_pin_config[] = {
GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH,
GPIO105_GPIO | MFP_LPM_DRIVE_HIGH, /* MMC/SD power */
GPIO53_GPIO, /* PC card reset */
GPIO102_GPIO, /* WLAN reset */
/* NAND controls */
GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */
......@@ -131,6 +141,7 @@ static unsigned long cmx270_pin_config[] = {
/* interrupts */
GPIO10_GPIO, /* DM9000 interrupt */
GPIO83_GPIO, /* MMC card detect */
GPIO95_GPIO, /* WLAN interrupt */
};
/* V3020 RTC */
......@@ -271,64 +282,114 @@ static inline void cmx270_init_ohci(void) {}
#endif
#if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE)
static int cmx270_mci_init(struct device *dev,
irq_handler_t cmx270_detect_int,
void *data)
static struct pxamci_platform_data cmx270_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.gpio_card_detect = GPIO83_MMC_IRQ,
.gpio_card_ro = -1,
.gpio_power = GPIO105_MMC_POWER,
.gpio_power_invert = 1,
};
static void __init cmx270_init_mmc(void)
{
int err;
pxa_set_mci_info(&cmx270_mci_platform_data);
}
#else
static inline void cmx270_init_mmc(void) {}
#endif
#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
static struct pxa2xx_spi_master cm_x270_spi_info = {
.num_chipselect = 1,
.enable_dma = 1,
};
static struct pxa2xx_spi_chip cm_x270_libertas_chip = {
.rx_threshold = 1,
.tx_threshold = 1,
.timeout = 1000,
.gpio_cs = 14,
};
static unsigned long cm_x270_libertas_pin_config[] = {
/* SSP2 */
GPIO19_SSP2_SCLK,
GPIO14_GPIO,
GPIO87_SSP2_TXD,
GPIO88_SSP2_RXD,
};
err = gpio_request(GPIO105_MMC_POWER, "MMC/SD power");
if (err) {
dev_warn(dev, "power gpio unavailable\n");
static int cm_x270_libertas_setup(struct spi_device *spi)
{
int err = gpio_request(GPIO19_WLAN_STRAP, "WLAN STRAP");
if (err)
return err;
}
gpio_direction_output(GPIO105_MMC_POWER, 0);
err = gpio_request(GPIO102_WLAN_RST, "WLAN RST");
if (err)
goto err_free_strap;
err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
gpio_free(GPIO105_MMC_POWER);
dev_err(dev, "cmx270_mci_init: MMC/SD: can't"
" request MMC card detect IRQ\n");
}
err = gpio_direction_output(GPIO102_WLAN_RST, 0);
if (err)
goto err_free_strap;
msleep(100);
err = gpio_direction_output(GPIO19_WLAN_STRAP, 1);
if (err)
goto err_free_strap;
msleep(100);
pxa2xx_mfp_config(ARRAY_AND_SIZE(cm_x270_libertas_pin_config));
gpio_set_value(GPIO102_WLAN_RST, 1);
msleep(100);
spi->bits_per_word = 16;
spi_setup(spi);
return 0;
err_free_strap:
gpio_free(GPIO19_WLAN_STRAP);
return err;
}
static void cmx270_mci_setpower(struct device *dev, unsigned int vdd)
static int cm_x270_libertas_teardown(struct spi_device *spi)
{
struct pxamci_platform_data *p_d = dev->platform_data;
if ((1 << vdd) & p_d->ocr_mask) {
dev_dbg(dev, "power on\n");
gpio_set_value(GPIO105_MMC_POWER, 0);
} else {
gpio_set_value(GPIO105_MMC_POWER, 1);
dev_dbg(dev, "power off\n");
}
}
gpio_set_value(GPIO102_WLAN_RST, 0);
gpio_free(GPIO102_WLAN_RST);
gpio_free(GPIO19_WLAN_STRAP);
static void cmx270_mci_exit(struct device *dev, void *data)
{
free_irq(CMX270_MMC_IRQ, data);
gpio_free(GPIO105_MMC_POWER);
return 0;
}
static struct pxamci_platform_data cmx270_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = cmx270_mci_init,
.setpower = cmx270_mci_setpower,
.exit = cmx270_mci_exit,
struct libertas_spi_platform_data cm_x270_libertas_pdata = {
.use_dummy_writes = 1,
.setup = cm_x270_libertas_setup,
.teardown = cm_x270_libertas_teardown,
};
static void __init cmx270_init_mmc(void)
static struct spi_board_info cm_x270_spi_devices[] __initdata = {
{
.modalias = "libertas_spi",
.max_speed_hz = 13000000,
.bus_num = 2,
.irq = gpio_to_irq(95),
.chip_select = 0,
.controller_data = &cm_x270_libertas_chip,
.platform_data = &cm_x270_libertas_pdata,
},
};
static void __init cmx270_init_spi(void)
{
pxa_set_mci_info(&cmx270_mci_platform_data);
pxa2xx_set_spi_info(2, &cm_x270_spi_info);
spi_register_board_info(ARRAY_AND_SIZE(cm_x270_spi_devices));
}
#else
static inline void cmx270_init_mmc(void) {}
static inline void cmx270_init_spi(void) {}
#endif
void __init cmx270_init(void)
......@@ -343,4 +404,5 @@ void __init cmx270_init(void)
cmx270_init_mmc();
cmx270_init_ohci();
cmx270_init_2700G();
cmx270_init_spi();
}
......@@ -306,68 +306,21 @@ static void cm_x300_mci_exit(struct device *dev, void *data)
}
static struct pxamci_platform_data cm_x300_mci_platform_data = {
.detect_delay = 20,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = cm_x300_mci_init,
.exit = cm_x300_mci_exit,
.detect_delay = 20,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = cm_x300_mci_init,
.exit = cm_x300_mci_exit,
.gpio_card_detect = -1,
.gpio_card_ro = -1,
.gpio_power = -1,
};
static int cm_x300_mci2_ro(struct device *dev)
{
return gpio_get_value(GPIO85_MMC2_WP);
}
static int cm_x300_mci2_init(struct device *dev,
irq_handler_t cm_x300_detect_int,
void *data)
{
int err;
/*
* setup GPIO for CM-X300 MMC controller
*/
err = gpio_request(GPIO82_MMC2_IRQ, "mmc card detect");
if (err)
goto err_request_cd;
gpio_direction_input(GPIO82_MMC2_IRQ);
err = gpio_request(GPIO85_MMC2_WP, "mmc write protect");
if (err)
goto err_request_wp;
gpio_direction_input(GPIO85_MMC2_WP);
err = request_irq(CM_X300_MMC2_IRQ, cm_x300_detect_int,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
printk(KERN_ERR "%s: MMC/SD/SDIO: "
"can't request card detect IRQ\n", __func__);
goto err_request_irq;
}
return 0;
err_request_irq:
gpio_free(GPIO85_MMC2_WP);
err_request_wp:
gpio_free(GPIO82_MMC2_IRQ);
err_request_cd:
return err;
}
static void cm_x300_mci2_exit(struct device *dev, void *data)
{
free_irq(CM_X300_MMC2_IRQ, data);
gpio_free(GPIO82_MMC2_IRQ);
gpio_free(GPIO85_MMC2_WP);
}
static struct pxamci_platform_data cm_x300_mci2_platform_data = {
.detect_delay = 20,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = cm_x300_mci2_init,
.exit = cm_x300_mci2_exit,
.get_ro = cm_x300_mci2_ro,
.detect_delay = 20,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.gpio_card_detect = GPIO82_MMC2_IRQ,
.gpio_card_ro = GPIO85_MMC2_WP,
.gpio_power = -1,
};
static void __init cm_x300_init_mmc(void)
......
......@@ -172,6 +172,7 @@ void __init colibri_pxa300_init(void)
{
colibri_pxa300_init_eth();
colibri_pxa300_init_ohci();
colibri_pxa3xx_init_nand();
colibri_pxa300_init_lcd();
colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO));
colibri_pxa310_init_ac97();
......
......@@ -164,15 +164,48 @@ static inline void __init colibri_pxa320_init_ac97(void)
static inline void colibri_pxa320_init_ac97(void) {}
#endif
/*
* The following configuration is verified to work with the Toradex Orchid
* carrier board
*/
static mfp_cfg_t colibri_pxa320_uart_pin_config[] __initdata = {
/* UART 1 configuration (may be set by bootloader) */
GPIO99_UART1_CTS,
GPIO104_UART1_RTS,
GPIO97_UART1_RXD,
GPIO98_UART1_TXD,
GPIO101_UART1_DTR,
GPIO103_UART1_DSR,
GPIO100_UART1_DCD,
GPIO102_UART1_RI,
/* UART 2 configuration */
GPIO109_UART2_CTS,
GPIO112_UART2_RTS,
GPIO110_UART2_RXD,
GPIO111_UART2_TXD,
/* UART 3 configuration */
GPIO30_UART3_RXD,
GPIO31_UART3_TXD,
};
static void __init colibri_pxa320_init_uart(void)
{
pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_uart_pin_config));
}
void __init colibri_pxa320_init(void)
{
colibri_pxa320_init_eth();
colibri_pxa320_init_ohci();
colibri_pxa3xx_init_nand();
colibri_pxa320_init_lcd();
colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO));
colibri_pxa320_init_ac97();
colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config),
mfp_to_gpio(MFP_PIN_GPIO28));
colibri_pxa320_init_uart();
}
MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
......
......@@ -25,6 +25,7 @@
#include <mach/colibri.h>
#include <mach/mmc.h>
#include <mach/pxafb.h>
#include <mach/pxa3xx_nand.h>
#include "generic.h"
#include "devices.h"
......@@ -95,10 +96,13 @@ static void colibri_pxa3xx_mci_exit(struct device *dev, void *data)
}
static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = {
.detect_delay = 20,
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.init = colibri_pxa3xx_mci_init,
.exit = colibri_pxa3xx_mci_exit,
.detect_delay = 20,
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.init = colibri_pxa3xx_mci_init,
.exit = colibri_pxa3xx_mci_exit,
.gpio_card_detect = -1,
.gpio_card_ro = -1,
.gpio_power = -1,
};
void __init colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin)
......@@ -154,3 +158,43 @@ void __init colibri_pxa3xx_init_lcd(int bl_pin)
}
#endif
#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
static struct mtd_partition colibri_nand_partitions[] = {
{
.name = "bootloader",
.offset = 0,
.size = SZ_512K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_4M,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
{
.name = "reserved",
.offset = MTDPART_OFS_APPEND,
.size = SZ_1M,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
{
.name = "fs",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct pxa3xx_nand_platform_data colibri_nand_info = {
.enable_arbiter = 1,
.keep_config = 1,
.parts = colibri_nand_partitions,
.nr_parts = ARRAY_SIZE(colibri_nand_partitions),
};
void __init colibri_pxa3xx_init_nand(void)
{
pxa3xx_set_nand_info(&colibri_nand_info);
}
#endif
......@@ -29,6 +29,7 @@
#include <linux/spi/ads7846.h>
#include <linux/spi/corgi_lcd.h>
#include <linux/mtd/sharpsl.h>
#include <linux/input/matrix_keypad.h>
#include <video/w100fb.h>
#include <asm/setup.h>
......@@ -104,6 +105,28 @@ static unsigned long corgi_pin_config[] __initdata = {
GPIO6_MMC_CLK,
GPIO8_MMC_CS0,
/* GPIO Matrix Keypad */
GPIO66_GPIO, /* column 0 */
GPIO67_GPIO, /* column 1 */
GPIO68_GPIO, /* column 2 */
GPIO69_GPIO, /* column 3 */
GPIO70_GPIO, /* column 4 */
GPIO71_GPIO, /* column 5 */
GPIO72_GPIO, /* column 6 */
GPIO73_GPIO, /* column 7 */
GPIO74_GPIO, /* column 8 */
GPIO75_GPIO, /* column 9 */
GPIO76_GPIO, /* column 10 */
GPIO77_GPIO, /* column 11 */
GPIO58_GPIO, /* row 0 */
GPIO59_GPIO, /* row 1 */
GPIO60_GPIO, /* row 2 */
GPIO61_GPIO, /* row 3 */
GPIO62_GPIO, /* row 4 */
GPIO63_GPIO, /* row 5 */
GPIO64_GPIO, /* row 6 */
GPIO65_GPIO, /* row 7 */
/* GPIO */
GPIO9_GPIO, /* CORGI_GPIO_nSD_DETECT */
GPIO7_GPIO, /* CORGI_GPIO_nSD_WP */
......@@ -267,9 +290,115 @@ static struct platform_device corgifb_device = {
/*
* Corgi Keyboard Device
*/
#define CORGI_KEY_CALENDER KEY_F1
#define CORGI_KEY_ADDRESS KEY_F2
#define CORGI_KEY_FN KEY_F3
#define CORGI_KEY_CANCEL KEY_F4
#define CORGI_KEY_OFF KEY_SUSPEND
#define CORGI_KEY_EXOK KEY_F5
#define CORGI_KEY_EXCANCEL KEY_F6
#define CORGI_KEY_EXJOGDOWN KEY_F7
#define CORGI_KEY_EXJOGUP KEY_F8
#define CORGI_KEY_JAP1 KEY_LEFTCTRL
#define CORGI_KEY_JAP2 KEY_LEFTALT
#define CORGI_KEY_MAIL KEY_F10
#define CORGI_KEY_OK KEY_F11
#define CORGI_KEY_MENU KEY_F12
static const uint32_t corgikbd_keymap[] = {
KEY(0, 1, KEY_1),
KEY(0, 2, KEY_3),
KEY(0, 3, KEY_5),
KEY(0, 4, KEY_6),
KEY(0, 5, KEY_7),
KEY(0, 6, KEY_9),
KEY(0, 7, KEY_0),
KEY(0, 8, KEY_BACKSPACE),
KEY(1, 1, KEY_2),
KEY(1, 2, KEY_4),
KEY(1, 3, KEY_R),
KEY(1, 4, KEY_Y),
KEY(1, 5, KEY_8),
KEY(1, 6, KEY_I),
KEY(1, 7, KEY_O),
KEY(1, 8, KEY_P),
KEY(2, 0, KEY_TAB),
KEY(2, 1, KEY_Q),
KEY(2, 2, KEY_E),
KEY(2, 3, KEY_T),
KEY(2, 4, KEY_G),
KEY(2, 5, KEY_U),
KEY(2, 6, KEY_J),
KEY(2, 7, KEY_K),
KEY(3, 0, CORGI_KEY_CALENDER),
KEY(3, 1, KEY_W),
KEY(3, 2, KEY_S),
KEY(3, 3, KEY_F),
KEY(3, 4, KEY_V),
KEY(3, 5, KEY_H),
KEY(3, 6, KEY_M),
KEY(3, 7, KEY_L),
KEY(3, 9, KEY_RIGHTSHIFT),
KEY(4, 0, CORGI_KEY_ADDRESS),
KEY(4, 1, KEY_A),
KEY(4, 2, KEY_D),
KEY(4, 3, KEY_C),
KEY(4, 4, KEY_B),
KEY(4, 5, KEY_N),
KEY(4, 6, KEY_DOT),
KEY(4, 8, KEY_ENTER),
KEY(4, 10, KEY_LEFTSHIFT),
KEY(5, 0, CORGI_KEY_MAIL),
KEY(5, 1, KEY_Z),
KEY(5, 2, KEY_X),
KEY(5, 3, KEY_MINUS),
KEY(5, 4, KEY_SPACE),
KEY(5, 5, KEY_COMMA),
KEY(5, 7, KEY_UP),
KEY(5, 11, CORGI_KEY_FN),
KEY(6, 0, KEY_SYSRQ),
KEY(6, 1, CORGI_KEY_JAP1),
KEY(6, 2, CORGI_KEY_JAP2),
KEY(6, 3, CORGI_KEY_CANCEL),
KEY(6, 4, CORGI_KEY_OK),
KEY(6, 5, CORGI_KEY_MENU),
KEY(6, 6, KEY_LEFT),
KEY(6, 7, KEY_DOWN),
KEY(6, 8, KEY_RIGHT),
KEY(7, 0, CORGI_KEY_OFF),
KEY(7, 1, CORGI_KEY_EXOK),
KEY(7, 2, CORGI_KEY_EXCANCEL),
KEY(7, 3, CORGI_KEY_EXJOGDOWN),
KEY(7, 4, CORGI_KEY_EXJOGUP),
};
static struct matrix_keymap_data corgikbd_keymap_data = {
.keymap = corgikbd_keymap,
.keymap_size = ARRAY_SIZE(corgikbd_keymap),
};
static const int corgikbd_row_gpios[] =
{ 58, 59, 60, 61, 62, 63, 64, 65 };
static const int corgikbd_col_gpios[] =
{ 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77 };
static struct matrix_keypad_platform_data corgikbd_pdata = {
.keymap_data = &corgikbd_keymap_data,
.row_gpios = corgikbd_row_gpios,
.col_gpios = corgikbd_col_gpios,
.num_row_gpios = ARRAY_SIZE(corgikbd_row_gpios),
.num_col_gpios = ARRAY_SIZE(corgikbd_col_gpios),
.col_scan_delay_us = 10,
.debounce_ms = 10,
.wakeup = 1,
};
static struct platform_device corgikbd_device = {
.name = "corgi-keyboard",
.name = "matrix-keypad",
.id = -1,
.dev = {
.platform_data = &corgikbd_pdata,
},
};
/*
......@@ -307,111 +436,20 @@ static struct platform_device corgiled_device = {
* The card detect interrupt isn't debounced so we delay it by 250ms
* to give the card a chance to fully insert/eject.
*/
static struct pxamci_platform_data corgi_mci_platform_data;
static int corgi_mci_init(struct device *dev, irq_handler_t corgi_detect_int, void *data)
{
int err;
err = gpio_request(CORGI_GPIO_nSD_DETECT, "nSD_DETECT");
if (err)
goto err_out;
err = gpio_request(CORGI_GPIO_nSD_WP, "nSD_WP");
if (err)
goto err_free_1;
err = gpio_request(CORGI_GPIO_SD_PWR, "SD_PWR");
if (err)
goto err_free_2;
gpio_direction_input(CORGI_GPIO_nSD_DETECT);
gpio_direction_input(CORGI_GPIO_nSD_WP);
gpio_direction_output(CORGI_GPIO_SD_PWR, 0);
corgi_mci_platform_data.detect_delay = msecs_to_jiffies(250);
err = request_irq(CORGI_IRQ_GPIO_nSD_DETECT, corgi_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
pr_err("%s: MMC/SD: can't request MMC card detect IRQ\n",
__func__);
goto err_free_3;
}
return 0;
err_free_3:
gpio_free(CORGI_GPIO_SD_PWR);
err_free_2:
gpio_free(CORGI_GPIO_nSD_WP);
err_free_1:
gpio_free(CORGI_GPIO_nSD_DETECT);
err_out:
return err;
}
static void corgi_mci_setpower(struct device *dev, unsigned int vdd)
{
struct pxamci_platform_data* p_d = dev->platform_data;
gpio_set_value(CORGI_GPIO_SD_PWR, ((1 << vdd) & p_d->ocr_mask));
}
static int corgi_mci_get_ro(struct device *dev)
{
return gpio_get_value(CORGI_GPIO_nSD_WP);
}
static void corgi_mci_exit(struct device *dev, void *data)
{
free_irq(CORGI_IRQ_GPIO_nSD_DETECT, data);
gpio_free(CORGI_GPIO_SD_PWR);
gpio_free(CORGI_GPIO_nSD_WP);
gpio_free(CORGI_GPIO_nSD_DETECT);
}
static struct pxamci_platform_data corgi_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = corgi_mci_init,
.get_ro = corgi_mci_get_ro,
.setpower = corgi_mci_setpower,
.exit = corgi_mci_exit,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.gpio_card_detect = -1,
.gpio_card_ro = CORGI_GPIO_nSD_WP,
.gpio_power = CORGI_GPIO_SD_PWR,
};
/*
* Irda
*/
static void corgi_irda_transceiver_mode(struct device *dev, int mode)
{
gpio_set_value(CORGI_GPIO_IR_ON, mode & IR_OFF);
pxa2xx_transceiver_mode(dev, mode);
}
static int corgi_irda_startup(struct device *dev)
{
int err;
err = gpio_request(CORGI_GPIO_IR_ON, "IR_ON");
if (err)
return err;
gpio_direction_output(CORGI_GPIO_IR_ON, 1);
return 0;
}
static void corgi_irda_shutdown(struct device *dev)
{
gpio_free(CORGI_GPIO_IR_ON);
}
static struct pxaficp_platform_data corgi_ficp_platform_data = {
.gpio_pwdown = CORGI_GPIO_IR_ON,
.transceiver_cap = IR_SIRMODE | IR_OFF,
.transceiver_mode = corgi_irda_transceiver_mode,
.startup = corgi_irda_startup,
.shutdown = corgi_irda_shutdown,
};
......@@ -636,6 +674,7 @@ static void __init corgi_init(void)
corgi_init_spi();
pxa_set_udc_info(&udc_info);
corgi_mci_platform_data.detect_delay = msecs_to_jiffies(250);
pxa_set_mci_info(&corgi_mci_platform_data);
pxa_set_ficp_info(&corgi_ficp_platform_data);
pxa_set_i2c_info(NULL);
......
......@@ -130,61 +130,17 @@ static struct pxamci_platform_data csb726_mci_data;
static int csb726_mci_init(struct device *dev,
irq_handler_t detect, void *data)
{
int err;
csb726_mci_data.detect_delay = msecs_to_jiffies(500);
err = gpio_request(CSB726_GPIO_MMC_DETECT, "MMC detect");
if (err)
goto err_det_req;
err = gpio_direction_input(CSB726_GPIO_MMC_DETECT);
if (err)
goto err_det_dir;
err = gpio_request(CSB726_GPIO_MMC_RO, "MMC ro");
if (err)
goto err_ro_req;
err = gpio_direction_input(CSB726_GPIO_MMC_RO);
if (err)
goto err_ro_dir;
err = request_irq(gpio_to_irq(CSB726_GPIO_MMC_DETECT), detect,
IRQF_DISABLED, "MMC card detect", data);
if (err)
goto err_irq;
return 0;
err_irq:
err_ro_dir:
gpio_free(CSB726_GPIO_MMC_RO);
err_ro_req:
err_det_dir:
gpio_free(CSB726_GPIO_MMC_DETECT);
err_det_req:
return err;
}
static int csb726_mci_get_ro(struct device *dev)
{
return gpio_get_value(CSB726_GPIO_MMC_RO);
}
static void csb726_mci_exit(struct device *dev, void *data)
{
free_irq(gpio_to_irq(CSB726_GPIO_MMC_DETECT), data);
gpio_free(CSB726_GPIO_MMC_RO);
gpio_free(CSB726_GPIO_MMC_DETECT);
}
static struct pxamci_platform_data csb726_mci = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = csb726_mci_init,
.get_ro = csb726_mci_get_ro,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.init = csb726_mci_init,
/* FIXME setpower */
.exit = csb726_mci_exit,
.gpio_card_detect = CSB726_GPIO_MMC_DETECT,
.gpio_card_ro = CSB726_GPIO_MMC_RO,
.gpio_power = -1,
};
static struct pxaohci_platform_data csb726_ohci_platform_data = {
......
......@@ -935,6 +935,33 @@ void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
{
pxa_register_device(&pxa3xx_device_nand, info);
}
static struct resource pxa3xx_resources_gcu[] = {
{
.start = 0x54000000,
.end = 0x54000fff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_GCU,
.end = IRQ_GCU,
.flags = IORESOURCE_IRQ,
},
};
static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
struct platform_device pxa3xx_device_gcu = {
.name = "pxa3xx-gcu",
.id = -1,
.num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
.resource = pxa3xx_resources_gcu,
.dev = {
.dma_mask = &pxa3xx_gcu_dmamask,
.coherent_dma_mask = 0xffffffff,
},
};
#endif /* CONFIG_PXA3xx */
/* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
......
......@@ -35,4 +35,6 @@ extern struct platform_device pxa27x_device_pwm1;
extern struct platform_device pxa3xx_device_nand;
extern struct platform_device pxa3xx_device_i2c_power;
extern struct platform_device pxa3xx_device_gcu;
void __init pxa_register_device(struct platform_device *dev, void *data);
......@@ -199,7 +199,6 @@ static void __init e740_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
pxa_set_udc_info(&e7xx_udc_mach_info);
pxa_set_ac97_info(NULL);
e7xx_irda_init();
pxa_set_ficp_info(&e7xx_ficp_platform_data);
}
......
......@@ -200,7 +200,6 @@ static void __init e750_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
pxa_set_udc_info(&e7xx_udc_mach_info);
pxa_set_ac97_info(NULL);
e7xx_irda_init();
pxa_set_ficp_info(&e7xx_ficp_platform_data);
}
......
......@@ -646,13 +646,16 @@ static int em_x270_mci_get_ro(struct device *dev)
}
static struct pxamci_platform_data em_x270_mci_platform_data = {
.ocr_mask = MMC_VDD_20_21|MMC_VDD_21_22|MMC_VDD_22_23|
MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27|
MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
MMC_VDD_30_31|MMC_VDD_31_32,
.init = em_x270_mci_init,
.setpower = em_x270_mci_setpower,
.exit = em_x270_mci_exit,
.ocr_mask = MMC_VDD_20_21|MMC_VDD_21_22|MMC_VDD_22_23|
MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27|
MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
MMC_VDD_30_31|MMC_VDD_31_32,
.init = em_x270_mci_init,
.setpower = em_x270_mci_setpower,
.exit = em_x270_mci_exit,
.gpio_card_detect = -1,
.gpio_card_ro = -1,
.gpio_power = -1,
};
static void __init em_x270_init_mmc(void)
......@@ -1022,22 +1025,32 @@ static int em_x270_sensor_power(struct device *dev, int on)
return 0;
}
static struct soc_camera_link iclink = {
.bus_id = 0,
.power = em_x270_sensor_power,
};
static struct i2c_board_info em_x270_i2c_cam_info[] = {
{
I2C_BOARD_INFO("mt9m111", 0x48),
},
};
static struct soc_camera_link iclink = {
.bus_id = 0,
.power = em_x270_sensor_power,
.board_info = &em_x270_i2c_cam_info[0],
.i2c_adapter_id = 0,
.module_name = "mt9m111",
};
static struct platform_device em_x270_camera = {
.name = "soc-camera-pdrv",
.id = -1,
.dev = {
.platform_data = &iclink,
},
};
static void __init em_x270_init_camera(void)
{
i2c_register_board_info(0, ARRAY_AND_SIZE(em_x270_i2c_cam_info));
pxa_set_camera_info(&em_x270_camera_platform_data);
platform_device_register(&em_x270_camera);
}
#else
static inline void em_x270_init_camera(void) {}
......@@ -1103,6 +1116,7 @@ REGULATOR_CONSUMER(ldo5, NULL, "vcc cam");
REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio");
REGULATOR_CONSUMER(ldo12, NULL, "vcc usb");
REGULATOR_CONSUMER(ldo19, &em_x270_gprs_userspace_consumer.dev, "vcc gprs");
REGULATOR_CONSUMER(buck2, NULL, "vcc_core");
#define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \
static struct regulator_init_data _ldo##_data = { \
......@@ -1125,6 +1139,7 @@ REGULATOR_INIT(ldo10, 2000000, 3200000,
REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE);
REGULATOR_INIT(ldo12, 3000000, 3000000, REGULATOR_CHANGE_STATUS);
REGULATOR_INIT(ldo19, 3200000, 3200000, REGULATOR_CHANGE_STATUS);
REGULATOR_INIT(buck2, 1000000, 1650000, REGULATOR_CHANGE_VOLTAGE);
struct led_info em_x270_led_info = {
.name = "em-x270:orange",
......@@ -1194,6 +1209,8 @@ struct da903x_subdev_info em_x270_da9030_subdevs[] = {
DA9030_LDO(12),
DA9030_LDO(19),
DA9030_SUBDEV(regulator, BUCK2, &buck2_data),
DA9030_SUBDEV(led, LED_PC, &em_x270_led_info),
DA9030_SUBDEV(backlight, WLED, &em_x270_led_info),
DA9030_SUBDEV(battery, BAT, &em_x270_batterty_info),
......@@ -1245,7 +1262,6 @@ static void __init em_x270_init_i2c(void)
static void __init em_x270_module_init(void)
{
pr_info("%s\n", __func__);
pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_pin_config));
mmc_cd = GPIO13_MMC_CD;
......@@ -1257,7 +1273,6 @@ static void __init em_x270_module_init(void)
static void __init em_x270_exeda_init(void)
{
pr_info("%s\n", __func__);
pxa2xx_mfp_config(ARRAY_AND_SIZE(exeda_pin_config));
mmc_cd = GPIO114_MMC_CD;
......
......@@ -47,44 +47,9 @@ struct pxa2xx_udc_mach_info e7xx_udc_mach_info = {
.gpio_pullup_inverted = 1
};
static void e7xx_irda_transceiver_mode(struct device *dev, int mode)
{
if (mode & IR_OFF) {
gpio_set_value(GPIO_E7XX_IR_OFF, 1);
pxa2xx_transceiver_mode(dev, mode);
} else {
pxa2xx_transceiver_mode(dev, mode);
gpio_set_value(GPIO_E7XX_IR_OFF, 0);
}
}
int e7xx_irda_init(void)
{
int ret;
ret = gpio_request(GPIO_E7XX_IR_OFF, "IrDA power");
if (ret)
goto out;
ret = gpio_direction_output(GPIO_E7XX_IR_OFF, 0);
if (ret)
goto out;
e7xx_irda_transceiver_mode(NULL, IR_SIRMODE | IR_OFF);
out:
return ret;
}
static void e7xx_irda_shutdown(struct device *dev)
{
e7xx_irda_transceiver_mode(dev, IR_SIRMODE | IR_OFF);
gpio_free(GPIO_E7XX_IR_OFF);
}
struct pxaficp_platform_data e7xx_ficp_platform_data = {
.transceiver_cap = IR_SIRMODE | IR_OFF,
.transceiver_mode = e7xx_irda_transceiver_mode,
.shutdown = e7xx_irda_shutdown,
.gpio_pwdown = GPIO_E7XX_IR_OFF,
.transceiver_cap = IR_SIRMODE | IR_OFF,
};
int eseries_tmio_enable(struct platform_device *dev)
......
......@@ -88,7 +88,10 @@ static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_MMC_PXA
static struct pxamci_platform_data gumstix_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.gpio_card_detect = -1,
.gpio_card_ro = -1,
.gpio_power = -1,
};
static void __init gumstix_mmc_init(void)
......
......@@ -45,6 +45,7 @@
#include <mach/irda.h>
#include <mach/pxa2xx_spi.h>
#include <video/platform_lcd.h>
#include <video/w100fb.h>
#include "devices.h"
......@@ -174,14 +175,9 @@ static int hx4700_gpio_request(struct gpio_ress *gpios, int size)
* IRDA
*/
static void irda_transceiver_mode(struct device *dev, int mode)
{
gpio_set_value(GPIO105_HX4700_nIR_ON, mode & IR_OFF);
}
static struct pxaficp_platform_data ficp_info = {
.transceiver_cap = IR_SIRMODE | IR_OFF,
.transceiver_mode = irda_transceiver_mode,
.gpio_pwdown = GPIO105_HX4700_nIR_ON,
.transceiver_cap = IR_SIRMODE | IR_OFF,
};
/*
......@@ -368,8 +364,6 @@ static struct platform_device egpio = {
* LCD - Sony display connected to ATI Imageon w3220
*/
static int lcd_power;
static void sony_lcd_init(void)
{
gpio_set_value(GPIO84_HX4700_LCD_SQN, 1);
......@@ -410,35 +404,6 @@ static void sony_lcd_off(void)
gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
}
static int hx4700_lcd_set_power(struct lcd_device *ldev, int level)
{
switch (level) {
case FB_BLANK_UNBLANK:
sony_lcd_init();
break;
case FB_BLANK_NORMAL:
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_POWERDOWN:
sony_lcd_off();
break;
}
lcd_power = level;
return 0;
}
static int hx4700_lcd_get_power(struct lcd_device *lm)
{
return lcd_power;
}
static struct lcd_ops hx4700_lcd_ops = {
.get_power = hx4700_lcd_get_power,
.set_power = hx4700_lcd_set_power,
};
static struct lcd_device *hx4700_lcd_device;
#ifdef CONFIG_PM
static void w3220_lcd_suspend(struct w100fb_par *wfb)
{
......@@ -573,6 +538,27 @@ static struct platform_device w3220 = {
.resource = w3220_resources,
};
static void hx4700_lcd_set_power(struct plat_lcd_data *pd, unsigned int power)
{
if (power)
sony_lcd_init();
else
sony_lcd_off();
}
static struct plat_lcd_data hx4700_lcd_data = {
.set_power = hx4700_lcd_set_power,
};
static struct platform_device hx4700_lcd = {
.name = "platform-lcd",
.id = -1,
.dev = {
.platform_data = &hx4700_lcd_data,
.parent = &w3220.dev,
},
};
/*
* Backlight
*/
......@@ -872,9 +858,6 @@ static void __init hx4700_init(void)
pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info));
hx4700_lcd_device = lcd_device_register("w100fb", NULL,
(void *)&w3220_info, &hx4700_lcd_ops);
gpio_set_value(GPIO71_HX4700_ASIC3_nRESET, 0);
mdelay(10);
gpio_set_value(GPIO71_HX4700_ASIC3_nRESET, 1);
......
......@@ -168,7 +168,10 @@ static struct pxafb_mach_info sharp_lm8v31 = {
};
static struct pxamci_platform_data idp_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.gpio_card_detect = -1,
.gpio_card_ro = -1,
.gpio_power = -1,
};
static void __init idp_init(void)
......
......@@ -389,6 +389,9 @@ static int imote2_mci_get_ro(struct device *dev)
static struct pxamci_platform_data imote2_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* default anyway */
.get_ro = imote2_mci_get_ro,
.gpio_card_detect = -1,
.gpio_card_ro = -1,
.gpio_power = -1,
};
static struct mtd_partition imote2flash_partitions[] = {
......
/*
* linux/include/asm-arm/arch-pxa/balloon3.h
*
* Authors: Nick Bane and Wookey
* Created: Oct, 2005
* Copyright: Toby Churchill Ltd
* Cribbed from mainstone.c, by Nicholas Pitre
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ASM_ARCH_BALLOON3_H
#define ASM_ARCH_BALLOON3_H
enum balloon3_features {
BALLOON3_FEATURE_OHCI,
BALLOON3_FEATURE_MMC,
BALLOON3_FEATURE_CF,
BALLOON3_FEATURE_AUDIO,
BALLOON3_FEATURE_TOPPOLY,
};
#define BALLOON3_FPGA_PHYS PXA_CS4_PHYS
#define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */
#define BALLOON3_FPGA_LENGTH 0x01000000
/* FPGA/CPLD registers */
#define BALLOON3_PCMCIA0_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
/* fixme - same for now */
#define BALLOON3_PCMCIA1_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
#define BALLOON3_NANDIO_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000)
/* fpga/cpld interrupt control register */
#define BALLOON3_INT_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e0000C)
#define BALLOON3_NANDIO_CTL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010)
#define BALLOON3_NANDIO_CTL_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
#define BALLOON3_VERSION_REG (BALLOON3_FPGA_VIRT + 0x00e0001c)
#define BALLOON3_SAMOSA_ADDR_REG (BALLOON3_FPGA_VIRT + 0x00c00000)
#define BALLOON3_SAMOSA_DATA_REG (BALLOON3_FPGA_VIRT + 0x00c00004)
#define BALLOON3_SAMOSA_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00c0001c)
/* GPIOs for irqs */
#define BALLOON3_GPIO_AUX_NIRQ (94)
#define BALLOON3_GPIO_CODEC_IRQ (95)
/* Timer and Idle LED locations */
#define BALLOON3_GPIO_LED_NAND (9)
#define BALLOON3_GPIO_LED_IDLE (10)
/* backlight control */
#define BALLOON3_GPIO_RUN_BACKLIGHT (99)
#define BALLOON3_GPIO_S0_CD (105)
/* FPGA Interrupt Mask/Acknowledge Register */
#define BALLOON3_INT_S0_IRQ (1 << 0) /* PCMCIA 0 IRQ */
#define BALLOON3_INT_S0_STSCHG (1 << 1) /* PCMCIA 0 status changed */
/* CF Status Register */
#define BALLOON3_PCMCIA_nIRQ (1 << 0) /* IRQ / ready signal */
#define BALLOON3_PCMCIA_nSTSCHG_BVD1 (1 << 1)
/* VDD sense / card status changed */
/* CF control register (write) */
#define BALLOON3_PCMCIA_RESET (1 << 0) /* Card reset signal */
#define BALLOON3_PCMCIA_ENABLE (1 << 1)
#define BALLOON3_PCMCIA_ADD_ENABLE (1 << 2)
/* CPLD (and FPGA) interface definitions */
#define CPLD_LCD0_DATA_SET 0x00
#define CPLD_LCD0_DATA_CLR 0x10
#define CPLD_LCD0_COMMAND_SET 0x01
#define CPLD_LCD0_COMMAND_CLR 0x11
#define CPLD_LCD1_DATA_SET 0x02
#define CPLD_LCD1_DATA_CLR 0x12
#define CPLD_LCD1_COMMAND_SET 0x03
#define CPLD_LCD1_COMMAND_CLR 0x13
#define CPLD_MISC_SET 0x07
#define CPLD_MISC_CLR 0x17
#define CPLD_MISC_LOON_NRESET_BIT 0
#define CPLD_MISC_LOON_UNSUSP_BIT 1
#define CPLD_MISC_RUN_5V_BIT 2
#define CPLD_MISC_CHG_D0_BIT 3
#define CPLD_MISC_CHG_D1_BIT 4
#define CPLD_MISC_DAC_NCS_BIT 5
#define CPLD_LCD_SET 0x08
#define CPLD_LCD_CLR 0x18
#define CPLD_LCD_BACKLIGHT_EN_0_BIT 0
#define CPLD_LCD_BACKLIGHT_EN_1_BIT 1
#define CPLD_LCD_LED_RED_BIT 4
#define CPLD_LCD_LED_GREEN_BIT 5
#define CPLD_LCD_NRESET_BIT 7
#define CPLD_LCD_RO_SET 0x09
#define CPLD_LCD_RO_CLR 0x19
#define CPLD_LCD_RO_LCD0_nWAIT_BIT 0
#define CPLD_LCD_RO_LCD1_nWAIT_BIT 1
#define CPLD_SERIAL_SET 0x0a
#define CPLD_SERIAL_CLR 0x1a
#define CPLD_SERIAL_GSM_RI_BIT 0
#define CPLD_SERIAL_GSM_CTS_BIT 1
#define CPLD_SERIAL_GSM_DTR_BIT 2
#define CPLD_SERIAL_LPR_CTS_BIT 3
#define CPLD_SERIAL_TC232_CTS_BIT 4
#define CPLD_SERIAL_TC232_DSR_BIT 5
#define CPLD_SROUTING_SET 0x0b
#define CPLD_SROUTING_CLR 0x1b
#define CPLD_SROUTING_MSP430_LPR 0
#define CPLD_SROUTING_MSP430_TC232 1
#define CPLD_SROUTING_MSP430_GSM 2
#define CPLD_SROUTING_LOON_LPR (0 << 4)
#define CPLD_SROUTING_LOON_TC232 (1 << 4)
#define CPLD_SROUTING_LOON_GSM (2 << 4)
#define CPLD_AROUTING_SET 0x0c
#define CPLD_AROUTING_CLR 0x1c
#define CPLD_AROUTING_MIC2PHONE_BIT 0
#define CPLD_AROUTING_PHONE2INT_BIT 1
#define CPLD_AROUTING_PHONE2EXT_BIT 2
#define CPLD_AROUTING_LOONL2INT_BIT 3
#define CPLD_AROUTING_LOONL2EXT_BIT 4
#define CPLD_AROUTING_LOONR2PHONE_BIT 5
#define CPLD_AROUTING_LOONR2INT_BIT 6
#define CPLD_AROUTING_LOONR2EXT_BIT 7
extern int balloon3_has(enum balloon3_features feature);
#endif
......@@ -23,6 +23,12 @@ static inline void colibri_pxa3xx_init_lcd(int bl_pin) {}
extern void colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data);
#endif
#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE)
extern void colibri_pxa3xx_init_nand(void);
#else
static inline void colibri_pxa3xx_init_nand(void) {}
#endif
/* physical memory regions */
#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */
......
......@@ -24,34 +24,27 @@
mov \tmp, \tmp, lsr #13
and \tmp, \tmp, #0x7 @ Core G
cmp \tmp, #1
bhi 1004f
bhi 1002f
@ Core Generation 1 (PXA25x)
mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
add \base, \base, #0x00d00000
ldr \irqstat, [\base, #0] @ ICIP
ldr \irqnr, [\base, #4] @ ICMR
b 1002f
1004:
mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2
mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2
ands \irqnr, \irqstat, \irqnr
beq 1003f
beq 1001f
rsb \irqstat, \irqnr, #0
and \irqstat, \irqstat, \irqnr
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #31
add \irqnr, \irqnr, #(32 + PXA_IRQ(0))
rsb \irqnr, \irqnr, #(31 + PXA_IRQ(0))
b 1001f
1003:
mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
1002:
ands \irqnr, \irqstat, \irqnr
@ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx)
mrc p6, 0, \irqstat, c5, c0, 0 @ ICHP
tst \irqstat, #0x80000000
beq 1001f
rsb \irqstat, \irqnr, #0
and \irqstat, \irqstat, \irqnr
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #(31 + PXA_IRQ(0))
bic \irqstat, \irqstat, #0x80000000
mov \irqnr, \irqstat, lsr #16
1001:
.endm
......@@ -197,6 +197,16 @@
#define __cpu_is_pxa935(id) (0)
#endif
#ifdef CONFIG_CPU_PXA950
#define __cpu_is_pxa950(id) \
({ \
unsigned int _id = (id) >> 4 & 0xfff; \
id == 0x697; \
})
#else
#define __cpu_is_pxa950(id) (0)
#endif
#define cpu_is_pxa210() \
({ \
__cpu_is_pxa210(read_cpuid_id()); \
......@@ -249,6 +259,13 @@
__cpu_is_pxa935(id); \
})
#define cpu_is_pxa950() \
({ \
unsigned int id = read_cpuid(CPUID_ID); \
__cpu_is_pxa950(id); \
})
/*
* CPUID Core Generation Bit
* <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
......
......@@ -12,6 +12,8 @@ struct pxaficp_platform_data {
void (*transceiver_mode)(struct device *dev, int mode);
int (*startup)(struct device *dev);
void (*shutdown)(struct device *dev);
int gpio_pwdown; /* powerdown GPIO for the IrDA chip */
bool gpio_pwdown_inverted; /* gpio_pwdown is inverted */
};
extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
......
......@@ -68,9 +68,10 @@
#ifdef CONFIG_PXA3xx
#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */
#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */
#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */
#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */
#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */
#define IRQ_GRPHICS PXA_IRQ(39) /* Graphics Controller */
#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller */
#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */
#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */
#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */
......@@ -81,8 +82,31 @@
#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
#endif
#define PXA_GPIO_IRQ_BASE PXA_IRQ(64)
#define PXA_GPIO_IRQ_NUM (128)
#ifdef CONFIG_CPU_PXA935
#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */
#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */
#define IRQ_MMC3_PXA935 PXA_IRQ(72) /* MMC3 Controller (PXA935) */
#define IRQ_MMC4_PXA935 PXA_IRQ(73) /* MMC4 Controller (PXA935) */
#define IRQ_MMC5_PXA935 PXA_IRQ(74) /* MMC5 Controller (PXA935) */
#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */
#endif
#ifdef CONFIG_CPU_PXA930
#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */
#define IRQ_ACIPC0 PXA_IRQ(5)
#define IRQ_ACIPC1 PXA_IRQ(40)
#define IRQ_ACIPC2 PXA_IRQ(19)
#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball */
#endif
#ifdef CONFIG_CPU_PXA950
#define IRQ_GC500 PXA_IRQ(70) /* Graphics Controller (PXA950) */
#endif
#define PXA_GPIO_IRQ_BASE PXA_IRQ(96)
#define PXA_GPIO_IRQ_NUM (192)
#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
......@@ -105,6 +129,8 @@
#define IRQ_BOARD_END (IRQ_BOARD_START + 70)
#elif defined(CONFIG_MACH_ZYLONITE)
#define IRQ_BOARD_END (IRQ_BOARD_START + 32)
#elif defined(CONFIG_PXA_EZX)
#define IRQ_BOARD_END (IRQ_BOARD_START + 23)
#else
#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
#endif
......@@ -237,6 +263,16 @@
#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
/* Balloon3 Interrupts */
#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x))
#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0)
#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1)
#define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ)
#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD)
/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0)
#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1)
......
......@@ -16,305 +16,6 @@
#ifndef __ASM_ARCH_MFP_H
#define __ASM_ARCH_MFP_H
#define mfp_to_gpio(m) ((m) % 128)
/* list of all the configurable MFP pins */
enum {
MFP_PIN_INVALID = -1,
MFP_PIN_GPIO0 = 0,
MFP_PIN_GPIO1,
MFP_PIN_GPIO2,
MFP_PIN_GPIO3,
MFP_PIN_GPIO4,
MFP_PIN_GPIO5,
MFP_PIN_GPIO6,
MFP_PIN_GPIO7,
MFP_PIN_GPIO8,
MFP_PIN_GPIO9,
MFP_PIN_GPIO10,
MFP_PIN_GPIO11,
MFP_PIN_GPIO12,
MFP_PIN_GPIO13,
MFP_PIN_GPIO14,
MFP_PIN_GPIO15,
MFP_PIN_GPIO16,
MFP_PIN_GPIO17,
MFP_PIN_GPIO18,
MFP_PIN_GPIO19,
MFP_PIN_GPIO20,
MFP_PIN_GPIO21,
MFP_PIN_GPIO22,
MFP_PIN_GPIO23,
MFP_PIN_GPIO24,
MFP_PIN_GPIO25,
MFP_PIN_GPIO26,
MFP_PIN_GPIO27,
MFP_PIN_GPIO28,
MFP_PIN_GPIO29,
MFP_PIN_GPIO30,
MFP_PIN_GPIO31,
MFP_PIN_GPIO32,
MFP_PIN_GPIO33,
MFP_PIN_GPIO34,
MFP_PIN_GPIO35,
MFP_PIN_GPIO36,
MFP_PIN_GPIO37,
MFP_PIN_GPIO38,
MFP_PIN_GPIO39,
MFP_PIN_GPIO40,
MFP_PIN_GPIO41,
MFP_PIN_GPIO42,
MFP_PIN_GPIO43,
MFP_PIN_GPIO44,
MFP_PIN_GPIO45,
MFP_PIN_GPIO46,
MFP_PIN_GPIO47,
MFP_PIN_GPIO48,
MFP_PIN_GPIO49,
MFP_PIN_GPIO50,
MFP_PIN_GPIO51,
MFP_PIN_GPIO52,
MFP_PIN_GPIO53,
MFP_PIN_GPIO54,
MFP_PIN_GPIO55,
MFP_PIN_GPIO56,
MFP_PIN_GPIO57,
MFP_PIN_GPIO58,
MFP_PIN_GPIO59,
MFP_PIN_GPIO60,
MFP_PIN_GPIO61,
MFP_PIN_GPIO62,
MFP_PIN_GPIO63,
MFP_PIN_GPIO64,
MFP_PIN_GPIO65,
MFP_PIN_GPIO66,
MFP_PIN_GPIO67,
MFP_PIN_GPIO68,
MFP_PIN_GPIO69,
MFP_PIN_GPIO70,
MFP_PIN_GPIO71,
MFP_PIN_GPIO72,
MFP_PIN_GPIO73,
MFP_PIN_GPIO74,
MFP_PIN_GPIO75,
MFP_PIN_GPIO76,
MFP_PIN_GPIO77,
MFP_PIN_GPIO78,
MFP_PIN_GPIO79,
MFP_PIN_GPIO80,
MFP_PIN_GPIO81,
MFP_PIN_GPIO82,
MFP_PIN_GPIO83,
MFP_PIN_GPIO84,
MFP_PIN_GPIO85,
MFP_PIN_GPIO86,
MFP_PIN_GPIO87,
MFP_PIN_GPIO88,
MFP_PIN_GPIO89,
MFP_PIN_GPIO90,
MFP_PIN_GPIO91,
MFP_PIN_GPIO92,
MFP_PIN_GPIO93,
MFP_PIN_GPIO94,
MFP_PIN_GPIO95,
MFP_PIN_GPIO96,
MFP_PIN_GPIO97,
MFP_PIN_GPIO98,
MFP_PIN_GPIO99,
MFP_PIN_GPIO100,
MFP_PIN_GPIO101,
MFP_PIN_GPIO102,
MFP_PIN_GPIO103,
MFP_PIN_GPIO104,
MFP_PIN_GPIO105,
MFP_PIN_GPIO106,
MFP_PIN_GPIO107,
MFP_PIN_GPIO108,
MFP_PIN_GPIO109,
MFP_PIN_GPIO110,
MFP_PIN_GPIO111,
MFP_PIN_GPIO112,
MFP_PIN_GPIO113,
MFP_PIN_GPIO114,
MFP_PIN_GPIO115,
MFP_PIN_GPIO116,
MFP_PIN_GPIO117,
MFP_PIN_GPIO118,
MFP_PIN_GPIO119,
MFP_PIN_GPIO120,
MFP_PIN_GPIO121,
MFP_PIN_GPIO122,
MFP_PIN_GPIO123,
MFP_PIN_GPIO124,
MFP_PIN_GPIO125,
MFP_PIN_GPIO126,
MFP_PIN_GPIO127,
MFP_PIN_GPIO0_2,
MFP_PIN_GPIO1_2,
MFP_PIN_GPIO2_2,
MFP_PIN_GPIO3_2,
MFP_PIN_GPIO4_2,
MFP_PIN_GPIO5_2,
MFP_PIN_GPIO6_2,
MFP_PIN_GPIO7_2,
MFP_PIN_GPIO8_2,
MFP_PIN_GPIO9_2,
MFP_PIN_GPIO10_2,
MFP_PIN_GPIO11_2,
MFP_PIN_GPIO12_2,
MFP_PIN_GPIO13_2,
MFP_PIN_GPIO14_2,
MFP_PIN_GPIO15_2,
MFP_PIN_GPIO16_2,
MFP_PIN_GPIO17_2,
MFP_PIN_ULPI_STP,
MFP_PIN_ULPI_NXT,
MFP_PIN_ULPI_DIR,
MFP_PIN_nXCVREN,
MFP_PIN_DF_CLE_nOE,
MFP_PIN_DF_nADV1_ALE,
MFP_PIN_DF_SCLK_E,
MFP_PIN_DF_SCLK_S,
MFP_PIN_nBE0,
MFP_PIN_nBE1,
MFP_PIN_DF_nADV2_ALE,
MFP_PIN_DF_INT_RnB,
MFP_PIN_DF_nCS0,
MFP_PIN_DF_nCS1,
MFP_PIN_nLUA,
MFP_PIN_nLLA,
MFP_PIN_DF_nWE,
MFP_PIN_DF_ALE_nWE,
MFP_PIN_DF_nRE_nOE,
MFP_PIN_DF_ADDR0,
MFP_PIN_DF_ADDR1,
MFP_PIN_DF_ADDR2,
MFP_PIN_DF_ADDR3,
MFP_PIN_DF_IO0,
MFP_PIN_DF_IO1,
MFP_PIN_DF_IO2,
MFP_PIN_DF_IO3,
MFP_PIN_DF_IO4,
MFP_PIN_DF_IO5,
MFP_PIN_DF_IO6,
MFP_PIN_DF_IO7,
MFP_PIN_DF_IO8,
MFP_PIN_DF_IO9,
MFP_PIN_DF_IO10,
MFP_PIN_DF_IO11,
MFP_PIN_DF_IO12,
MFP_PIN_DF_IO13,
MFP_PIN_DF_IO14,
MFP_PIN_DF_IO15,
/* additional pins on PXA930 */
MFP_PIN_GSIM_UIO,
MFP_PIN_GSIM_UCLK,
MFP_PIN_GSIM_UDET,
MFP_PIN_GSIM_nURST,
MFP_PIN_PMIC_INT,
MFP_PIN_RDY,
MFP_PIN_MAX,
};
/*
* a possible MFP configuration is represented by a 32-bit integer
*
* bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
* bit 10..12 - Alternate Function Selection
* bit 13..15 - Drive Strength
* bit 16..18 - Low Power Mode State
* bit 19..20 - Low Power Mode Edge Detection
* bit 21..22 - Run Mode Pull State
*
* to facilitate the definition, the following macros are provided
*
* MFP_CFG_DEFAULT - default MFP configuration value, with
* alternate function = 0,
* drive strength = fast 3mA (MFP_DS03X)
* low power mode = default
* edge detection = none
*
* MFP_CFG - default MFPR value with alternate function
* MFP_CFG_DRV - default MFPR value with alternate function and
* pin drive strength
* MFP_CFG_LPM - default MFPR value with alternate function and
* low power mode
* MFP_CFG_X - default MFPR value with alternate function,
* pin drive strength and low power mode
*/
typedef unsigned long mfp_cfg_t;
#define MFP_PIN(x) ((x) & 0x3ff)
#define MFP_AF0 (0x0 << 10)
#define MFP_AF1 (0x1 << 10)
#define MFP_AF2 (0x2 << 10)
#define MFP_AF3 (0x3 << 10)
#define MFP_AF4 (0x4 << 10)
#define MFP_AF5 (0x5 << 10)
#define MFP_AF6 (0x6 << 10)
#define MFP_AF7 (0x7 << 10)
#define MFP_AF_MASK (0x7 << 10)
#define MFP_AF(x) (((x) >> 10) & 0x7)
#define MFP_DS01X (0x0 << 13)
#define MFP_DS02X (0x1 << 13)
#define MFP_DS03X (0x2 << 13)
#define MFP_DS04X (0x3 << 13)
#define MFP_DS06X (0x4 << 13)
#define MFP_DS08X (0x5 << 13)
#define MFP_DS10X (0x6 << 13)
#define MFP_DS13X (0x7 << 13)
#define MFP_DS_MASK (0x7 << 13)
#define MFP_DS(x) (((x) >> 13) & 0x7)
#define MFP_LPM_DEFAULT (0x0 << 16)
#define MFP_LPM_DRIVE_LOW (0x1 << 16)
#define MFP_LPM_DRIVE_HIGH (0x2 << 16)
#define MFP_LPM_PULL_LOW (0x3 << 16)
#define MFP_LPM_PULL_HIGH (0x4 << 16)
#define MFP_LPM_FLOAT (0x5 << 16)
#define MFP_LPM_INPUT (0x6 << 16)
#define MFP_LPM_STATE_MASK (0x7 << 16)
#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7)
#define MFP_LPM_EDGE_NONE (0x0 << 19)
#define MFP_LPM_EDGE_RISE (0x1 << 19)
#define MFP_LPM_EDGE_FALL (0x2 << 19)
#define MFP_LPM_EDGE_BOTH (0x3 << 19)
#define MFP_LPM_EDGE_MASK (0x3 << 19)
#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3)
#define MFP_PULL_NONE (0x0 << 21)
#define MFP_PULL_LOW (0x1 << 21)
#define MFP_PULL_HIGH (0x2 << 21)
#define MFP_PULL_BOTH (0x3 << 21)
#define MFP_PULL_MASK (0x3 << 21)
#define MFP_PULL(x) (((x) >> 21) & 0x3)
#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\
MFP_LPM_EDGE_NONE | MFP_PULL_NONE)
#define MFP_CFG(pin, af) \
((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af))
#define MFP_CFG_DRV(pin, af, drv) \
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv))
#define MFP_CFG_LPM(pin, af, lpm) \
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm))
#define MFP_CFG_X(pin, af, drv, lpm) \
((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
(MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
#include <plat/mfp.h>
#endif /* __ASM_ARCH_MFP_H */
......@@ -14,6 +14,11 @@ struct pxamci_platform_data {
int (*get_ro)(struct device *);
void (*setpower)(struct device *, unsigned int);
void (*exit)(struct device *, void *);
int gpio_card_detect; /* gpio detecting card insertion */
int gpio_card_ro; /* gpio detecting read only toggle */
bool gpio_card_ro_invert; /* gpio ro is inverted */
int gpio_power; /* gpio powering up MMC bus */
bool gpio_power_invert; /* gpio power is inverted */
};
extern void pxa_set_mci_info(struct pxamci_platform_data *info);
......
/*
* linux/include/asm-arm/arch-pxa/palmtc-gpio.h
*
* GPIOs and interrupts for Palm Tungsten|C Handheld Computer
*
* Authors: Alex Osborne <bobofdoom@gmail.com>
* Marek Vasut <marek.vasut@gmail.com>
* Holger Bocklet <bitz.email@gmx.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _INCLUDE_PALMTC_H_
#define _INCLUDE_PALMTC_H_
/** HERE ARE GPIOs **/
/* GPIOs */
#define GPIO_NR_PALMTC_EARPHONE_DETECT 2
#define GPIO_NR_PALMTC_CRADLE_DETECT 5
#define GPIO_NR_PALMTC_HOTSYNC_BUTTON 7
/* SD/MMC */
#define GPIO_NR_PALMTC_SD_DETECT_N 12
#define GPIO_NR_PALMTC_SD_POWER 32
#define GPIO_NR_PALMTC_SD_READONLY 54
/* WLAN */
#define GPIO_NR_PALMTC_PCMCIA_READY 13
#define GPIO_NR_PALMTC_PCMCIA_PWRREADY 14
#define GPIO_NR_PALMTC_PCMCIA_POWER1 15
#define GPIO_NR_PALMTC_PCMCIA_POWER2 33
#define GPIO_NR_PALMTC_PCMCIA_POWER3 55
#define GPIO_NR_PALMTC_PCMCIA_RESET 78
/* UDC */
#define GPIO_NR_PALMTC_USB_DETECT_N 4
#define GPIO_NR_PALMTC_USB_POWER 36
/* LCD/BACKLIGHT */
#define GPIO_NR_PALMTC_BL_POWER 16
#define GPIO_NR_PALMTC_LCD_POWER 44
#define GPIO_NR_PALMTC_LCD_BLANK 38
/* UART */
#define GPIO_NR_PALMTC_RS232_POWER 37
/* IRDA */
#define GPIO_NR_PALMTC_IR_DISABLE 45
/* IRQs */
#define IRQ_GPIO_PALMTC_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMTC_SD_DETECT_N)
#define IRQ_GPIO_PALMTC_WLAN_READY IRQ_GPIO(GPIO_NR_PALMTC_WLAN_READY)
/* UCB1400 GPIOs */
#define GPIO_NR_PALMTC_POWER_DETECT (0x80 | 0x00)
#define GPIO_NR_PALMTC_HEADPHONE_DETECT (0x80 | 0x01)
#define GPIO_NR_PALMTC_SPEAKER_ENABLE (0x80 | 0x03)
#define GPIO_NR_PALMTC_VIBRA_POWER (0x80 | 0x05)
#define GPIO_NR_PALMTC_LED_POWER (0x80 | 0x07)
/** HERE ARE INIT VALUES **/
#define PALMTC_UCB1400_GPIO_OFFSET 0x80
/* BATTERY */
#define PALMTC_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */
#define PALMTC_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */
#define PALMTC_BAT_MAX_CURRENT 0 /* unknokn */
#define PALMTC_BAT_MIN_CURRENT 0 /* unknown */
#define PALMTC_BAT_MAX_CHARGE 1 /* unknown */
#define PALMTC_BAT_MIN_CHARGE 1 /* unknown */
#define PALMTC_MAX_LIFE_MINS 240 /* on-life in minutes */
#define PALMTC_BAT_MEASURE_DELAY (HZ * 1)
/* BACKLIGHT */
#define PALMTC_MAX_INTENSITY 0xFE
#define PALMTC_DEFAULT_INTENSITY 0x7E
#define PALMTC_LIMIT_MASK 0x7F
#define PALMTC_PRESCALER 0x3F
#define PALMTC_PERIOD_NS 3500
#endif
......@@ -82,6 +82,11 @@
#define PALMTX_PHYS_FLASH_START PXA_CS0_PHYS /* ChipSelect 0 */
#define PALMTX_PHYS_NAND_START PXA_CS1_PHYS /* ChipSelect 1 */
#define PALMTX_NAND_ALE_PHYS (PALMTX_PHYS_NAND_START | (1 << 24))
#define PALMTX_NAND_CLE_PHYS (PALMTX_PHYS_NAND_START | (1 << 25))
#define PALMTX_NAND_ALE_VIRT 0xff100000
#define PALMTX_NAND_CLE_VIRT 0xff200000
/* TOUCHSCREEN */
#define AC97_LINK_FRAME 21
......
......@@ -208,7 +208,7 @@
#define CKEN_MVED 43 /* < MVED clock enable */
/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */
#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */
#define CKEN_PXA300_GCU 42 /* Graphics controller clock enable */
#define CKEN_PXA320_GCU 7 /* Graphics controller clock enable */
#endif /* __ASM_ARCH_PXA3XX_REGS_H */
......@@ -118,7 +118,8 @@ struct pxafb_mach_info {
u_int fixed_modes:1,
cmap_inverse:1,
cmap_static:1,
unused:29;
acceleration_enabled:1,
unused:28;
/* The following should be defined in LCCR0
* LCCR0_Act or LCCR0_Pas Active or Passive
......
......@@ -13,6 +13,7 @@
#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
......@@ -20,4 +21,14 @@
#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
#define ICIP3 __REG(0x40D00130) /* Interrupt Controller IRQ Pending Register 3 */
#define ICMR3 __REG(0x40D00134) /* Interrupt Controller Mask Register 3 */
#define ICLR3 __REG(0x40D00138) /* Interrupt Controller Level Register 3 */
#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */
#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */
#define IPR(x) __REG(0x40D0001C + (x < 32 ? (x << 2) \
: (x < 64 ? (0x94 + ((x - 32) << 2)) \
: (0x128 + ((x - 64) << 2)))))
#endif /* __ASM_MACH_REGS_INTC_H */
......@@ -37,7 +37,7 @@ static inline void arch_decomp_setup(void)
{
if (machine_is_littleton() || machine_is_intelmote2()
|| machine_is_csb726() || machine_is_stargate2()
|| machine_is_cm_x300())
|| machine_is_cm_x300() || machine_is_balloon3())
UART = STUART;
}
......
......@@ -120,7 +120,7 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
void __init pxa_init_irq(int irq_nr, set_wake_t fn)
{
int irq;
int irq, i;
pxa_internal_irq_nr = irq_nr;
......@@ -129,6 +129,12 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
_ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
}
/* initialize interrupt priority */
if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
for (i = 0; i < irq_nr; i++)
IPR(i) = i | (1 << 31);
}
/* only unmasked interrupts kick us out of idle */
ICCR = 1;
......
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