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Commit 0fec53a2 authored by Russell King's avatar Russell King Committed by Russell King
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[ARM] Remove EPXA10DB machine support 

EPXA10DB seems to be uncared for:
- the "PLD" code has never been merged
- no one has reported that this platform has been broken since
  at least 2.6.10
- interest seems to have dried up around March 2003.

Therefore, remove EPXA10DB support.
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b9abaa3f
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Showing with 2 additions and 4973 deletions
arch/arm/Kconfig
View file @ 0fec53a2
...@@ -103,13 +103,6 @@ config ARCH_EBSA110 ...@@ -103,13 +103,6 @@ config ARCH_EBSA110
Ethernet interface, two PCMCIA sockets, two serial ports and a Ethernet interface, two PCMCIA sockets, two serial ports and a
parallel port. parallel port.
config ARCH_CAMELOT
bool "Epxa10db"
help
This enables support for Altera's Excalibur XA10 development board.
If you would like to build your kernel to run on one of these boards
then you must say 'Y' here. Otherwise say 'N'
config ARCH_FOOTBRIDGE config ARCH_FOOTBRIDGE
bool "FootBridge" bool "FootBridge"
select FOOTBRIDGE select FOOTBRIDGE
...@@ -221,8 +214,6 @@ endchoice ...@@ -221,8 +214,6 @@ endchoice
source "arch/arm/mach-clps711x/Kconfig" source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-epxa10db/Kconfig"
source "arch/arm/mach-footbridge/Kconfig" source "arch/arm/mach-footbridge/Kconfig"
source "arch/arm/mach-integrator/Kconfig" source "arch/arm/mach-integrator/Kconfig"
......
arch/arm/Makefile
View file @ 0fec53a2
...@@ -84,7 +84,6 @@ endif ...@@ -84,7 +84,6 @@ endif
machine-$(CONFIG_ARCH_PXA) := pxa machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_L7200) := l7200 machine-$(CONFIG_ARCH_L7200) := l7200
machine-$(CONFIG_ARCH_INTEGRATOR) := integrator machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
machine-$(CONFIG_ARCH_CAMELOT) := epxa10db
textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
machine-$(CONFIG_ARCH_CLPS711X) := clps711x machine-$(CONFIG_ARCH_CLPS711X) := clps711x
machine-$(CONFIG_ARCH_IOP3XX) := iop3xx machine-$(CONFIG_ARCH_IOP3XX) := iop3xx
......
arch/arm/boot/compressed/Makefile
View file @ 0fec53a2
...@@ -21,10 +21,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y) ...@@ -21,10 +21,6 @@ ifeq ($(CONFIG_ARCH_SHARK),y)
OBJS += head-shark.o ofw-shark.o OBJS += head-shark.o ofw-shark.o
endif endif
ifeq ($(CONFIG_ARCH_CAMELOT),y)
OBJS += head-epxa10db.o
endif
ifeq ($(CONFIG_ARCH_L7200),y) ifeq ($(CONFIG_ARCH_L7200),y)
OBJS += head-l7200.o OBJS += head-l7200.o
endif endif
......
arch/arm/boot/compressed/head-epxa10db.S deleted 100644 → 0
View file @ b9abaa3f
#include <asm/mach-types.h>
#include <asm/arch/excalibur.h>
.section ".start", "ax"
mov r7, #MACH_TYPE_CAMELOT
arch/arm/configs/epxa10db_defconfig deleted 100644 → 0
View file @ b9abaa3f
This diff is collapsed.
arch/arm/mach-epxa10db/Kconfig deleted 100644 → 0
View file @ b9abaa3f
if ARCH_CAMELOT
menu "Epxa10db"
comment "PLD hotswap support"
config PLD
bool
default y
config PLD_HOTSWAP
bool "Support for PLD device hotplugging (experimental)"
depends on EXPERIMENTAL
help
This enables support for the dynamic loading and configuration of
compatible drivers when the contents of the PLD are changed. This
is still experimental and requires configuration tools which are
not yet generally available. Say N here. You must enable the kernel
module loader for this feature to work.
endmenu
endif
arch/arm/mach-epxa10db/Makefile deleted 100644 → 0
View file @ b9abaa3f
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y := arch.o irq.o mm.o time.o
obj-m :=
obj-n :=
obj- :=
arch/arm/mach-epxa10db/arch.c deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/arch/arm/mach-epxa10db/arch.c
*
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/serial_8250.h>
#include <asm/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static struct plat_serial8250_port serial_platform_data[] = {
{
.iobase = 0x3f8,
.irq = IRQ_UARTINT0,
#error FIXME
.uartclk = 0,
.regshift = 0,
.iotype = UPIO_PORT,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
},
{
.iobase = 0x2f8,
.irq = IRQ_UARTINT1,
#error FIXME
.uartclk = 0,
.regshift = 0,
.iotype = UPIO_PORT,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
},
{ },
};
static struct platform_device serial_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = serial_platform_data,
},
};
extern void epxa10db_map_io(void);
extern void epxa10db_init_irq(void);
extern struct sys_timer epxa10db_timer;
MACHINE_START(CAMELOT, "Altera Epxa10db")
/* Maintainer: Altera Corporation */
.phys_ram = 0x00000000,
.phys_io = 0x7fffc000,
.io_pg_offst = ((0xffffc000) >> 18) & 0xfffc,
.map_io = epxa10db_map_io,
.init_irq = epxa10db_init_irq,
.timer = &epxa10db_timer,
MACHINE_END
arch/arm/mach-epxa10db/irq.c deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/arch/arm/mach-epxa10db/irq.c
*
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/stddef.h>
#include <linux/timer.h>
#include <linux/list.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/arch/platform.h>
#include <asm/arch/int_ctrl00.h>
static void epxa_mask_irq(unsigned int irq)
{
writel(1 << irq, INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
}
static void epxa_unmask_irq(unsigned int irq)
{
writel(1 << irq, INT_MS(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
}
static struct irqchip epxa_irq_chip = {
.ack = epxa_mask_irq,
.mask = epxa_mask_irq,
.unmask = epxa_unmask_irq,
};
static struct resource irq_resource = {
.name = "irq_handler",
.start = IO_ADDRESS(EXC_INT_CTRL00_BASE),
.end = IO_ADDRESS(INT_PRIORITY_FC(EXC_INT_CTRL00_BASE))+4,
};
void __init epxa10db_init_irq(void)
{
unsigned int i;
request_resource(&iomem_resource, &irq_resource);
/*
* This bit sets up the interrupt controller using
* the 6 PLD interrupts mode (the default) each
* irqs is assigned a priority which is the same
* as its interrupt number. This scheme is used because
* its easy, but you may want to change it depending
* on the contents of your PLD
*/
writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
for (i = 0; i < NR_IRQS; i++){
writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i));
set_irq_chip(i,&epxa_irq_chip);
set_irq_handler(i,do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* Disable all interrupts */
writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
}
arch/arm/mach-epxa10db/mm.c deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/arch/arm/mach-epxa10db/mm.c
*
* MM routines for Altera'a Epxa10db board
*
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/sizes.h>
#include <asm/page.h>
#include <asm/mach/map.h>
/* Page table mapping for I/O region */
static struct map_desc epxa10db_io_desc[] __initdata = {
{
.virtual = IO_ADDRESS(EXC_REGISTERS_BASE),
.pfn = __phys_to_pfn(EXC_REGISTERS_BASE),
.length = SZ_16K,
.type = MT_DEVICE
}, {
.virtual = IO_ADDRESS(EXC_PLD_BLOCK0_BASE),
.pfn = __phys_to_pfn(EXC_PLD_BLOCK0_BASE),
.length = SZ_16K,
.type = MT_DEVICE
}, {
.virtual = IO_ADDRESS(EXC_PLD_BLOCK1_BASE),
.pfn =__phys_to_pfn(EXC_PLD_BLOCK1_BASE),
.length = SZ_16K,
.type = MT_DEVICE
}, {
.virtual = IO_ADDRESS(EXC_PLD_BLOCK2_BASE),
.physical = __phys_to_pfn(EXC_PLD_BLOCK2_BASE),
.length = SZ_16K,
.type = MT_DEVICE
}, {
.virtual = IO_ADDRESS(EXC_PLD_BLOCK3_BASE),
.pfn = __phys_to_pfn(EXC_PLD_BLOCK3_BASE),
.length = SZ_16K,
.type = MT_DEVICE
}, {
.virtual = FLASH_VADDR(EXC_EBI_BLOCK0_BASE),
.pfn = __phys_to_pfn(EXC_EBI_BLOCK0_BASE),
.length = SZ_16M,
.type = MT_DEVICE
}
};
void __init epxa10db_map_io(void)
{
iotable_init(epxa10db_io_desc, ARRAY_SIZE(epxa10db_io_desc));
}
arch/arm/mach-epxa10db/time.c deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/arch/arm/mach-epxa10db/time.c
*
* Copyright (C) 2000 Deep Blue Solutions
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <asm/hardware.h>
#include <asm/system.h>
#include <asm/leds.h>
#include <asm/mach/time.h>
#define TIMER00_TYPE (volatile unsigned int*)
#include <asm/arch/timer00.h>
static int epxa10db_set_rtc(void)
{
return 1;
}
static int epxa10db_rtc_init(void)
{
set_rtc = epxa10db_set_rtc;
return 0;
}
__initcall(epxa10db_rtc_init);
/*
* IRQ handler for the timer
*/
static irqreturn_t
epxa10db_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
write_seqlock(&xtime_lock);
// ...clear the interrupt
*TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))|=TIMER0_CR_CI_MSK;
timer_tick(regs);
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
static struct irqaction epxa10db_timer_irq = {
.name = "Excalibur Timer Tick",
.flags = SA_INTERRUPT | SA_TIMER,
.handler = epxa10db_timer_interrupt,
};
/*
* Set up timer interrupt, and return the current time in seconds.
*/
static void __init epxa10db_timer_init(void)
{
/* Start the timer */
*TIMER0_LIMIT(IO_ADDRESS(EXC_TIMER00_BASE))=(unsigned int)(EXC_AHB2_CLK_FREQUENCY/200);
*TIMER0_PRESCALE(IO_ADDRESS(EXC_TIMER00_BASE))=1;
*TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))=TIMER0_CR_IE_MSK | TIMER0_CR_S_MSK;
setup_irq(IRQ_TIMER0, &epxa10db_timer_irq);
}
struct sys_timer epxa10db_timer = {
.init = epxa10db_timer_init,
};
arch/arm/mm/Kconfig
View file @ 0fec53a2
...@@ -83,8 +83,8 @@ config CPU_ARM920T ...@@ -83,8 +83,8 @@ config CPU_ARM920T
# ARM922T # ARM922T
config CPU_ARM922T config CPU_ARM922T
bool "Support ARM922T processor" if ARCH_INTEGRATOR bool "Support ARM922T processor" if ARCH_INTEGRATOR
depends on ARCH_CAMELOT || ARCH_LH7A40X || ARCH_INTEGRATOR depends on ARCH_LH7A40X || ARCH_INTEGRATOR
default y if ARCH_CAMELOT || ARCH_LH7A40X default y if ARCH_LH7A40X
select CPU_32v4 select CPU_32v4
select CPU_ABRT_EV4T select CPU_ABRT_EV4T
select CPU_CACHE_V4WT select CPU_CACHE_V4WT
......
drivers/mtd/maps/Kconfig
View file @ 0fec53a2
...@@ -473,14 +473,6 @@ config MTD_IXP2000 ...@@ -473,14 +473,6 @@ config MTD_IXP2000
IXDP425 and Coyote. If you have an IXP2000 based board and IXDP425 and Coyote. If you have an IXP2000 based board and
would like to use the flash chips on it, say 'Y'. would like to use the flash chips on it, say 'Y'.
config MTD_EPXA10DB
tristate "CFI Flash device mapped on Epxa10db"
depends on MTD_CFI && MTD_PARTITIONS && ARCH_CAMELOT
help
This enables support for the flash devices on the Altera
Excalibur XA10 Development Board. If you are building a kernel
for on of these boards then you should say 'Y' otherwise say 'N'.
config MTD_FORTUNET config MTD_FORTUNET
tristate "CFI Flash device mapped on the FortuNet board" tristate "CFI Flash device mapped on the FortuNet board"
depends on MTD_CFI && MTD_PARTITIONS && SA1100_FORTUNET depends on MTD_CFI && MTD_PARTITIONS && SA1100_FORTUNET
......
drivers/mtd/maps/Makefile
View file @ 0fec53a2
...@@ -15,7 +15,6 @@ obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o ...@@ -15,7 +15,6 @@ obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
obj-$(CONFIG_MTD_CSTM_MIPS_IXX) += cstm_mips_ixx.o obj-$(CONFIG_MTD_CSTM_MIPS_IXX) += cstm_mips_ixx.o
obj-$(CONFIG_MTD_DC21285) += dc21285.o obj-$(CONFIG_MTD_DC21285) += dc21285.o
obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o
obj-$(CONFIG_MTD_EPXA10DB) += epxa10db-flash.o
obj-$(CONFIG_MTD_IQ80310) += iq80310.o obj-$(CONFIG_MTD_IQ80310) += iq80310.o
obj-$(CONFIG_MTD_L440GX) += l440gx.o obj-$(CONFIG_MTD_L440GX) += l440gx.o
obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o
......
drivers/mtd/maps/epxa10db-flash.c deleted 100644 → 0
View file @ b9abaa3f
/*
* Flash memory access on EPXA based devices
*
* (C) 2000 Nicolas Pitre <nico@cam.org>
* Copyright (C) 2001 Altera Corporation
* Copyright (C) 2001 Red Hat, Inc.
*
* $Id: epxa10db-flash.c,v 1.15 2005/11/07 11:14:27 gleixner Exp $
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <asm/io.h>
#include <asm/hardware.h>
#ifdef CONFIG_EPXA10DB
#define BOARD_NAME "EPXA10DB"
#else
#define BOARD_NAME "EPXA1DB"
#endif
static int nr_parts = 0;
static struct mtd_partition *parts;
static struct mtd_info *mymtd;
static int epxa_default_partitions(struct mtd_info *master, struct mtd_partition **pparts);
static struct map_info epxa_map = {
.name = "EPXA flash",
.size = FLASH_SIZE,
.bankwidth = 2,
.phys = FLASH_START,
};
static const char *probes[] = { "RedBoot", "afs", NULL };
static int __init epxa_mtd_init(void)
{
int i;
printk(KERN_NOTICE "%s flash device: 0x%x at 0x%x\n", BOARD_NAME, FLASH_SIZE, FLASH_START);
epxa_map.virt = ioremap(FLASH_START, FLASH_SIZE);
if (!epxa_map.virt) {
printk("Failed to ioremap %s flash\n",BOARD_NAME);
return -EIO;
}
simple_map_init(&epxa_map);
mymtd = do_map_probe("cfi_probe", &epxa_map);
if (!mymtd) {
iounmap((void *)epxa_map.virt);
return -ENXIO;
}
mymtd->owner = THIS_MODULE;
/* Unlock the flash device. */
if(mymtd->unlock){
for (i=0; i<mymtd->numeraseregions;i++){
int j;
for(j=0;j<mymtd->eraseregions[i].numblocks;j++){
mymtd->unlock(mymtd,mymtd->eraseregions[i].offset + j * mymtd->eraseregions[i].erasesize,mymtd->eraseregions[i].erasesize);
}
}
}
#ifdef CONFIG_MTD_PARTITIONS
nr_parts = parse_mtd_partitions(mymtd, probes, &parts, 0);
if (nr_parts > 0) {
add_mtd_partitions(mymtd, parts, nr_parts);
return 0;
}
#endif
/* No recognised partitioning schemes found - use defaults */
nr_parts = epxa_default_partitions(mymtd, &parts);
if (nr_parts > 0) {
add_mtd_partitions(mymtd, parts, nr_parts);
return 0;
}
/* If all else fails... */
add_mtd_device(mymtd);
return 0;
}
static void __exit epxa_mtd_cleanup(void)
{
if (mymtd) {
if (nr_parts)
del_mtd_partitions(mymtd);
else
del_mtd_device(mymtd);
map_destroy(mymtd);
}
if (epxa_map.virt) {
iounmap((void *)epxa_map.virt);
epxa_map.virt = 0;
}
}
/*
* This will do for now, once we decide which bootldr we're finally
* going to use then we'll remove this function and do it properly
*
* Partions are currently (as offsets from base of flash):
* 0x00000000 - 0x003FFFFF - bootloader (!)
* 0x00400000 - 0x00FFFFFF - Flashdisk
*/
static int __init epxa_default_partitions(struct mtd_info *master, struct mtd_partition **pparts)
{
struct mtd_partition *parts;
int ret, i;
int npartitions = 0;
char *names;
const char *name = "jffs";
printk("Using default partitions for %s\n",BOARD_NAME);
npartitions=1;
parts = kmalloc(npartitions*sizeof(*parts)+strlen(name), GFP_KERNEL);
memzero(parts,npartitions*sizeof(*parts)+strlen(name));
if (!parts) {
ret = -ENOMEM;
goto out;
}
i=0;
names = (char *)&parts[npartitions];
parts[i].name = names;
names += strlen(name) + 1;
strcpy(parts[i].name, name);
#ifdef CONFIG_EPXA10DB
parts[i].size = FLASH_SIZE-0x00400000;
parts[i].offset = 0x00400000;
#else
parts[i].size = FLASH_SIZE-0x00180000;
parts[i].offset = 0x00180000;
#endif
out:
*pparts = parts;
return npartitions;
}
module_init(epxa_mtd_init);
module_exit(epxa_mtd_cleanup);
MODULE_AUTHOR("Clive Davies");
MODULE_DESCRIPTION("Altera epxa mtd flash map");
MODULE_LICENSE("GPL");
drivers/net/arm/Kconfig
View file @ 0fec53a2
...@@ -31,16 +31,3 @@ config ARM_ETHERH ...@@ -31,16 +31,3 @@ config ARM_ETHERH
help help
If you have an Acorn system with one of these network cards, you If you have an Acorn system with one of these network cards, you
should say Y to this option if you wish to use it with Linux. should say Y to this option if you wish to use it with Linux.
config ARM_ETHER00
tristate "Altera Ether00 support"
depends on NET_ETHERNET && ARM && ARCH_CAMELOT
help
This is the driver for Altera's ether00 ethernet mac IP core. Say
Y here if you want to build support for this into the kernel. It
is also available as a module (say M here) that can be inserted/
removed from the kernel at the same time as the PLD is configured.
If this driver is running on an epxa10 development board then it
will generate a suitable hw address based on the board serial
number (MTD support is required for this). Otherwise you will
need to set a suitable hw address using ifconfig.
drivers/net/arm/Makefile
View file @ 0fec53a2
...@@ -4,7 +4,6 @@ ...@@ -4,7 +4,6 @@
# #
obj-$(CONFIG_ARM_AM79C961A) += am79c961a.o obj-$(CONFIG_ARM_AM79C961A) += am79c961a.o
obj-$(CONFIG_ARM_ETHER00) += ether00.o
obj-$(CONFIG_ARM_ETHERH) += etherh.o obj-$(CONFIG_ARM_ETHERH) += etherh.o
obj-$(CONFIG_ARM_ETHER3) += ether3.o obj-$(CONFIG_ARM_ETHER3) += ether3.o
obj-$(CONFIG_ARM_ETHER1) += ether1.o obj-$(CONFIG_ARM_ETHER1) += ether1.o
drivers/net/arm/ether00.c deleted 100644 → 0
View file @ b9abaa3f
This diff is collapsed.
drivers/serial/Kconfig
View file @ 0fec53a2
...@@ -359,29 +359,6 @@ config SERIAL_21285_CONSOLE ...@@ -359,29 +359,6 @@ config SERIAL_21285_CONSOLE
your boot loader (lilo or loadlin) about how to pass options to the your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.) kernel at boot time.)
config SERIAL_UART00
bool "Excalibur serial port (uart00) support"
depends on ARM && ARCH_CAMELOT
select SERIAL_CORE
help
Say Y here if you want to use the hard logic uart on Excalibur. This
driver also supports soft logic implementations of this uart core.
config SERIAL_UART00_CONSOLE
bool "Support for console on Excalibur serial port"
depends on SERIAL_UART00
select SERIAL_CORE_CONSOLE
help
Say Y here if you want to support a serial console on an Excalibur
hard logic uart or uart00 IP core.
Even if you say Y here, the currently visible virtual console
(/dev/tty0) will still be used as the system console by default, but
you can alter that using a kernel command line option such as
"console=ttyS1". (Try "man bootparam" or see the documentation of
your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.)
config SERIAL_MPSC config SERIAL_MPSC
bool "Marvell MPSC serial port support" bool "Marvell MPSC serial port support"
depends on PPC32 && MV64X60 depends on PPC32 && MV64X60
......
drivers/serial/Makefile
View file @ 0fec53a2
...@@ -29,7 +29,6 @@ obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o ...@@ -29,7 +29,6 @@ obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
obj-$(CONFIG_SERIAL_PXA) += pxa.o obj-$(CONFIG_SERIAL_PXA) += pxa.o
obj-$(CONFIG_SERIAL_SA1100) += sa1100.o obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
obj-$(CONFIG_SERIAL_UART00) += uart00.o
obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
......
drivers/serial/uart00.c deleted 100644 → 0
View file @ b9abaa3f
This diff is collapsed.
include/asm-arm/arch-epxa10db/debug-macro.S deleted 100644 → 0
View file @ b9abaa3f
/* linux/include/asm-arm/arch-epxa10db/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <asm/arch/excalibur.h>
#define UART00_TYPE
#include <asm/arch/uart00.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldr \rx, =EXC_UART00_BASE @ physical base address
orrne \rx, \rx, #0xff000000 @ virtual base
orrne \rx, \rx, #0x00f00000
.endm
.macro senduart,rd,rx
str \rd, [\rx, #UART_TD(0)]
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #UART_TSR(0)]
and \rd, \rd, #UART_TSR_TX_LEVEL_MSK
cmp \rd, #15
beq 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #UART_TSR(0)]
ands \rd, \rd, #UART_TSR_TX_LEVEL_MSK
bne 1001b
.endm
include/asm-arm/arch-epxa10db/dma.h deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/include/asm-arm/arch-camelot/dma.h
*
* Copyright (C) 1997,1998 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
include/asm-arm/arch-epxa10db/entry-macro.S deleted 100644 → 0
View file @ b9abaa3f
/*
* include/asm-arm/arch-epxa10db/entry-macro.S
*
* Low-level IRQ helper macros for epxa10db platform
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/arch/platform.h>
#undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */
#include <asm/arch/int_ctrl00.h>
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE))
ldr \irqnr,[\irqstat]
cmp \irqnr,#0
subne \irqnr,\irqnr,#1
.endm
include/asm-arm/arch-epxa10db/ether00.h deleted 100644 → 0
View file @ b9abaa3f
This diff is collapsed.
include/asm-arm/arch-epxa10db/excalibur.h deleted 100644 → 0
View file @ b9abaa3f
/* megafunction wizard: %ARM-Based Excalibur%
GENERATION: STANDARD
VERSION: WM1.0
MODULE: ARM-Based Excalibur
PROJECT: excalibur
============================================================
File Name: v:\embedded\linux\bootldr\excalibur.h
Megafunction Name(s): ARM-Based Excalibur
============================================================
************************************************************
THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
************************************************************/
#ifndef EXCALIBUR_H_INCLUDED
#define EXCALIBUR_H_INCLUDED
#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN
#define EXC_DEFINE_BOOT_FROM_FLASH
#define EXC_INPUT_CLK_FREQUENCY (50000000)
#define EXC_AHB1_CLK_FREQUENCY (150000000)
#define EXC_AHB2_CLK_FREQUENCY (75000000)
#define EXC_SDRAM_CLK_FREQUENCY (75000000)
/* Registers Block */
#define EXC_REGISTERS_BASE (0x7fffc000)
#define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000)
#define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040)
#define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080)
#define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140)
#define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200)
#define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00)
#define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300)
#define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00)
#define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280)
#define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380)
#define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400)
#define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800)
#define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
#define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
#define EXC_REGISTERS_SIZE (0x00004000)
/* EBI Block(s) */
#define EXC_EBI_BLOCK0_BASE (0x40000000)
#define EXC_EBI_BLOCK0_SIZE (0x00400000)
#define EXC_EBI_BLOCK0_WIDTH (8)
#define EXC_EBI_BLOCK0_NON_CACHEABLE
#define EXC_EBI_BLOCK1_BASE (0x40400000)
#define EXC_EBI_BLOCK1_SIZE (0x00400000)
#define EXC_EBI_BLOCK1_WIDTH (16)
#define EXC_EBI_BLOCK1_NON_CACHEABLE
#define EXC_EBI_BLOCK2_BASE (0x40800000)
#define EXC_EBI_BLOCK2_SIZE (0x00400000)
#define EXC_EBI_BLOCK2_WIDTH (16)
#define EXC_EBI_BLOCK2_NON_CACHEABLE
#define EXC_EBI_BLOCK3_BASE (0x40c00000)
#define EXC_EBI_BLOCK3_SIZE (0x00400000)
#define EXC_EBI_BLOCK3_WIDTH (16)
#define EXC_EBI_BLOCK3_NON_CACHEABLE
/* SDRAM Block(s) */
#define EXC_SDRAM_BLOCK0_BASE (0x00000000)
#define EXC_SDRAM_BLOCK0_SIZE (0x04000000)
#define EXC_SDRAM_BLOCK0_WIDTH (32)
#define EXC_SDRAM_BLOCK1_BASE (0x04000000)
#define EXC_SDRAM_BLOCK1_SIZE (0x04000000)
#define EXC_SDRAM_BLOCK1_WIDTH (32)
/* Single Port SRAM Block(s) */
#define EXC_SPSRAM_BLOCK0_BASE (0x08000000)
#define EXC_SPSRAM_BLOCK0_SIZE (0x00020000)
#define EXC_SPSRAM_BLOCK1_BASE (0x08020000)
#define EXC_SPSRAM_BLOCK1_SIZE (0x00020000)
/* PLD Block(s) */
#define EXC_PLD_BLOCK0_BASE (0x80000000)
#define EXC_PLD_BLOCK0_SIZE (0x00004000)
#define EXC_PLD_BLOCK0_NON_CACHEABLE
#define EXC_PLD_BLOCK1_BASE (0xf000000)
#define EXC_PLD_BLOCK1_SIZE (0x00004000)
#define EXC_PLD_BLOCK1_NON_CACHEABLE
#define EXC_PLD_BLOCK2_BASE (0x80008000)
#define EXC_PLD_BLOCK2_SIZE (0x00004000)
#define EXC_PLD_BLOCK2_NON_CACHEABLE
#define EXC_PLD_BLOCK3_BASE (0x8000c000)
#define EXC_PLD_BLOCK3_SIZE (0x00004000)
#define EXC_PLD_BLOCK3_NON_CACHEABLE
#endif
include/asm-arm/arch-epxa10db/hardware.h deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/include/asm-arm/arch-epxa10/hardware.h
*
* This file contains the hardware definitions of the Integrator.
*
* Copyright (C) 1999 ARM Limited.
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/arch/platform.h>
/*
* Where in virtual memory the IO devices (timers, system controllers
* and so on)
*/
#define IO_BASE 0xf0000000 // VA of IO
#define IO_SIZE 0x10000000 // How much?
#define IO_START EXC_REGISTERS_BASE // PA of IO
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) ((x) | 0xf0000000)
#define FLASH_VBASE 0xFE000000
#define FLASH_SIZE 0x01000000
#define FLASH_START EXC_EBI_BLOCK0_BASE
#define FLASH_VADDR(x) ((x)|0xFE000000)
/*
* Similar to above, but for PCI addresses (memory, IO, Config and the
* V3 chip itself). WARNING: this has to mirror definitions in platform.h
*/
#if 0
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_CONFIG_VADDR 0xec000000
#define PCI_V3_VADDR 0xed000000
#define PCI_IO_VADDR 0xee000000
#define PCIO_BASE PCI_IO_VADDR
#define PCIMEM_BASE PCI_MEMORY_VADDR
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x6000
#define PCIBIOS_MIN_MEM 0x00100000
#endif
#endif
include/asm-arm/arch-epxa10db/int_ctrl00.h deleted 100644 → 0
View file @ b9abaa3f
/*
*
* This file contains the register definitions for the Excalibur
* Timer TIMER00.
*
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __INT_CTRL00_H
#define __INT_CTRL00_H
#define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x00 ))
#define INT_MS_FC_MSK (0x10000)
#define INT_MS_FC_OFST (16)
#define INT_MS_M1_MSK (0x8000)
#define INT_MS_M1_OFST (15)
#define INT_MS_M0_MSK (0x4000)
#define INT_MS_M0_OFST (14)
#define INT_MS_AE_MSK (0x2000)
#define INT_MS_AE_OFST (13)
#define INT_MS_PE_MSK (0x1000)
#define INT_MS_PE_OFST (12)
#define INT_MS_EE_MSK (0x0800)
#define INT_MS_EE_OFST (11)
#define INT_MS_PS_MSK (0x0400)
#define INT_MS_PS_OFST (10)
#define INT_MS_T1_MSK (0x0200)
#define INT_MS_T1_OFST (9)
#define INT_MS_T0_MSK (0x0100)
#define INT_MS_T0_OFST (8)
#define INT_MS_UA_MSK (0x0080)
#define INT_MS_UA_OFST (7)
#define INT_MS_IP_MSK (0x0040)
#define INT_MS_IP_OFST (6)
#define INT_MS_P5_MSK (0x0020)
#define INT_MS_P5_OFST (5)
#define INT_MS_P4_MSK (0x0010)
#define INT_MS_P4_OFST (4)
#define INT_MS_P3_MSK (0x0008)
#define INT_MS_P3_OFST (3)
#define INT_MS_P2_MSK (0x0004)
#define INT_MS_P2_OFST (2)
#define INT_MS_P1_MSK (0x0002)
#define INT_MS_P1_OFST (1)
#define INT_MS_P0_MSK (0x0001)
#define INT_MS_P0_OFST (0)
#define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr + 0x04 ))
#define INT_MC_FC_MSK (0x10000)
#define INT_MC_FC_OFST (16)
#define INT_MC_M1_MSK (0x8000)
#define INT_MC_M1_OFST (15)
#define INT_MC_M0_MSK (0x4000)
#define INT_MC_M0_OFST (14)
#define INT_MC_AE_MSK (0x2000)
#define INT_MC_AE_OFST (13)
#define INT_MC_PE_MSK (0x1000)
#define INT_MC_PE_OFST (12)
#define INT_MC_EE_MSK (0x0800)
#define INT_MC_EE_OFST (11)
#define INT_MC_PS_MSK (0x0400)
#define INT_MC_PS_OFST (10)
#define INT_MC_T1_MSK (0x0200)
#define INT_MC_T1_OFST (9)
#define INT_MC_T0_MSK (0x0100)
#define INT_MC_T0_OFST (8)
#define INT_MC_UA_MSK (0x0080)
#define INT_MC_UA_OFST (7)
#define INT_MC_IP_MSK (0x0040)
#define INT_MC_IP_OFST (6)
#define INT_MC_P5_MSK (0x0020)
#define INT_MC_P5_OFST (5)
#define INT_MC_P4_MSK (0x0010)
#define INT_MC_P4_OFST (4)
#define INT_MC_P3_MSK (0x0008)
#define INT_MC_P3_OFST (3)
#define INT_MC_P2_MSK (0x0004)
#define INT_MC_P2_OFST (2)
#define INT_MC_P1_MSK (0x0002)
#define INT_MC_P1_OFST (1)
#define INT_MC_P0_MSK (0x0001)
#define INT_MC_P0_OFST (0)
#define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x08 ))
#define INT_SS_FC_SSK (0x8000)
#define INT_SS_FC_OFST (15)
#define INT_SS_M1_SSK (0x8000)
#define INT_SS_M1_OFST (15)
#define INT_SS_M0_SSK (0x4000)
#define INT_SS_M0_OFST (14)
#define INT_SS_AE_SSK (0x2000)
#define INT_SS_AE_OFST (13)
#define INT_SS_PE_SSK (0x1000)
#define INT_SS_PE_OFST (12)
#define INT_SS_EE_SSK (0x0800)
#define INT_SS_EE_OFST (11)
#define INT_SS_PS_SSK (0x0400)
#define INT_SS_PS_OFST (10)
#define INT_SS_T1_SSK (0x0200)
#define INT_SS_T1_OFST (9)
#define INT_SS_T0_SSK (0x0100)
#define INT_SS_T0_OFST (8)
#define INT_SS_UA_SSK (0x0080)
#define INT_SS_UA_OFST (7)
#define INT_SS_IP_SSK (0x0040)
#define INT_SS_IP_OFST (6)
#define INT_SS_P5_SSK (0x0020)
#define INT_SS_P5_OFST (5)
#define INT_SS_P4_SSK (0x0010)
#define INT_SS_P4_OFST (4)
#define INT_SS_P3_SSK (0x0008)
#define INT_SS_P3_OFST (3)
#define INT_SS_P2_SSK (0x0004)
#define INT_SS_P2_OFST (2)
#define INT_SS_P1_SSK (0x0002)
#define INT_SS_P1_OFST (1)
#define INT_SS_P0_SSK (0x0001)
#define INT_SS_P0_OFST (0)
#define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x0C ))
#define INT_RS_FC_RSK (0x10000)
#define INT_RS_FC_OFST (16)
#define INT_RS_M1_RSK (0x8000)
#define INT_RS_M1_OFST (15)
#define INT_RS_M0_RSK (0x4000)
#define INT_RS_M0_OFST (14)
#define INT_RS_AE_RSK (0x2000)
#define INT_RS_AE_OFST (13)
#define INT_RS_PE_RSK (0x1000)
#define INT_RS_PE_OFST (12)
#define INT_RS_EE_RSK (0x0800)
#define INT_RS_EE_OFST (11)
#define INT_RS_PS_RSK (0x0400)
#define INT_RS_PS_OFST (10)
#define INT_RS_T1_RSK (0x0200)
#define INT_RS_T1_OFST (9)
#define INT_RS_T0_RSK (0x0100)
#define INT_RS_T0_OFST (8)
#define INT_RS_UA_RSK (0x0080)
#define INT_RS_UA_OFST (7)
#define INT_RS_IP_RSK (0x0040)
#define INT_RS_IP_OFST (6)
#define INT_RS_P5_RSK (0x0020)
#define INT_RS_P5_OFST (5)
#define INT_RS_P4_RSK (0x0010)
#define INT_RS_P4_OFST (4)
#define INT_RS_P3_RSK (0x0008)
#define INT_RS_P3_OFST (3)
#define INT_RS_P2_RSK (0x0004)
#define INT_RS_P2_OFST (2)
#define INT_RS_P1_RSK (0x0002)
#define INT_RS_P1_OFST (1)
#define INT_RS_P0_RSK (0x0001)
#define INT_RS_P0_OFST (0)
#define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr + 0x10 ))
#define INT_ID_ID_MSK (0x3F)
#define INT_ID_ID_OFST (0)
#define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr + 0x14 ))
#define INT_PLD_PRIORITY_PRI_MSK (0x3F)
#define INT_PLD_PRIORITY_PRI_OFST (0)
#define INT_PLD_PRIORITY_GA_MSK (0x40)
#define INT_PLD_PRIORITY_GA_OFST (6)
#define INT_MODE(base_addr) (INT_CTRL00_TYPE (base_addr + 0x18 ))
#define INT_MODE_MODE_MSK (0x3)
#define INT_MODE_MODE_OFST (0)
#define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr + 0x80 ))
#define INT_PRIORITY_P0_PRI_MSK (0x3F)
#define INT_PRIORITY_P0_PRI_OFST (0)
#define INT_PRIORITY_P0_FQ_MSK (0x40)
#define INT_PRIORITY_P0_FQ_OFST (6)
#define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr + 0x84 ))
#define INT_PRIORITY_P1_PRI_MSK (0x3F)
#define INT_PRIORITY_P1_PRI_OFST (0)
#define INT_PRIORITY_P1_FQ_MSK (0x40)
#define INT_PRIORITY_P1_FQ_OFST (6)
#define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr + 0x88 ))
#define INT_PRIORITY_P2_PRI_MSK (0x3F)
#define INT_PRIORITY_P2_PRI_OFST (0)
#define INT_PRIORITY_P2_FQ_MSK (0x40)
#define INT_PRIORITY_P2_FQ_OFST (6)
#define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr + 0x8C ))
#define INT_PRIORITY_P3_PRI_MSK (0x3F)
#define INT_PRIORITY_P3_PRI_OFST (0)
#define INT_PRIORITY_P3_FQ_MSK (0x40)
#define INT_PRIORITY_P3_FQ_OFST (6)
#define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr + 0x90 ))
#define INT_PRIORITY_P4_PRI_MSK (0x3F)
#define INT_PRIORITY_P4_PRI_OFST (0)
#define INT_PRIORITY_P4_FQ_MSK (0x40)
#define INT_PRIORITY_P4_FQ_OFST (6)
#define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 ))
#define INT_PRIORITY_P5_PRI_MSK (0x3F)
#define INT_PRIORITY_P5_PRI_OFST (0)
#define INT_PRIORITY_P5_FQ_MSK (0x40)
#define INT_PRIORITY_P5_FQ_OFST (6)
#define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 ))
#define INT_PRIORITY_IP_PRI_MSK (0x3F)
#define INT_PRIORITY_IP_PRI_OFST (0)
#define INT_PRIORITY_IP_FQ_MSK (0x40)
#define INT_PRIORITY_IP_FQ_OFST (6)
#define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr + 0x9C ))
#define INT_PRIORITY_UA_PRI_MSK (0x3F)
#define INT_PRIORITY_UA_PRI_OFST (0)
#define INT_PRIORITY_UA_FQ_MSK (0x40)
#define INT_PRIORITY_UA_FQ_OFST (6)
#define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA0 ))
#define INT_PRIORITY_T0_PRI_MSK (0x3F)
#define INT_PRIORITY_T0_PRI_OFST (0)
#define INT_PRIORITY_T0_FQ_MSK (0x40)
#define INT_PRIORITY_T0_FQ_OFST (6)
#define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA4 ))
#define INT_PRIORITY_T1_PRI_MSK (0x3F)
#define INT_PRIORITY_T1_PRI_OFST (0)
#define INT_PRIORITY_T1_FQ_MSK (0x40)
#define INT_PRIORITY_T1_FQ_OFST (6)
#define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA8 ))
#define INT_PRIORITY_PS_PRI_MSK (0x3F)
#define INT_PRIORITY_PS_PRI_OFST (0)
#define INT_PRIORITY_PS_FQ_MSK (0x40)
#define INT_PRIORITY_PS_FQ_OFST (6)
#define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xAC ))
#define INT_PRIORITY_EE_PRI_MSK (0x3F)
#define INT_PRIORITY_EE_PRI_OFST (0)
#define INT_PRIORITY_EE_FQ_MSK (0x40)
#define INT_PRIORITY_EE_FQ_OFST (6)
#define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB0 ))
#define INT_PRIORITY_PE_PRI_MSK (0x3F)
#define INT_PRIORITY_PE_PRI_OFST (0)
#define INT_PRIORITY_PE_FQ_MSK (0x40)
#define INT_PRIORITY_PE_FQ_OFST (6)
#define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB4 ))
#define INT_PRIORITY_AE_PRI_MSK (0x3F)
#define INT_PRIORITY_AE_PRI_OFST (0)
#define INT_PRIORITY_AE_FQ_MSK (0x40)
#define INT_PRIORITY_AE_FQ_OFST (6)
#define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB8 ))
#define INT_PRIORITY_M0_PRI_MSK (0x3F)
#define INT_PRIORITY_M0_PRI_OFST (0)
#define INT_PRIORITY_M0_FQ_MSK (0x40)
#define INT_PRIORITY_M0_FQ_OFST (6)
#define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xBC ))
#define INT_PRIORITY_M1_PRI_MSK (0x3F)
#define INT_PRIORITY_M1_PRI_OFST (0)
#define INT_PRIORITY_M1_FQ_MSK (0x40)
#define INT_PRIORITY_M1_FQ_OFST (6)
#define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr + 0xC0 ))
#define INT_PRIORITY_FC_PRI_MSK (0x3F)
#define INT_PRIORITY_FC_PRI_OFST (0)
#define INT_PRIORITY_FC_FQ_MSK (0x40)
#define INT_PRIORITY_FC_FQ_OFST (6)
#endif /* __INT_CTRL00_H */
include/asm-arm/arch-epxa10db/io.h deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/include/asm-arm/arch-epxa10db/io.h
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffff
/*
* Generic virtual read/write
*/
/*#define outsw __arch_writesw
#define outsl __arch_writesl
#define outsb __arch_writesb
#define insb __arch_readsb
#define insw __arch_readsw
#define insl __arch_readsl*/
#define __io(a) ((void __iomem *)(a))
#define __mem_pci(a) (a)
#endif
include/asm-arm/arch-epxa10db/irqs.h deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/include/asm-arm/arch-camelot/irqs.h
*
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* Use the Excalibur chip definitions */
#define INT_CTRL00_TYPE
#include "asm/arch/int_ctrl00.h"
#define IRQ_PLD0 INT_MS_P0_OFST
#define IRQ_PLD1 INT_MS_P1_OFST
#define IRQ_PLD2 INT_MS_P2_OFST
#define IRQ_PLD3 INT_MS_P3_OFST
#define IRQ_PLD4 INT_MS_P4_OFST
#define IRQ_PLD5 INT_MS_P5_OFST
#define IRQ_EXT INT_MS_IP_OFST
#define IRQ_UART INT_MS_UA_OFST
#define IRQ_TIMER0 INT_MS_T0_OFST
#define IRQ_TIMER1 INT_MS_T1_OFST
#define IRQ_PLL INT_MS_PLL_OFST
#define IRQ_EBI INT_MS_EBI_OFST
#define IRQ_STRIPE_BRIDGE INT_MS_PLL_OFST
#define IRQ_AHB_BRIDGE INT_MS_PLL_OFST
#define IRQ_COMMRX INT_MS_CR_OFST
#define IRQ_COMMTX INT_MS_CT_OFST
#define IRQ_FAST_COMM INT_MS_FC_OFST
#define NR_IRQS (INT_MS_FC_OFST + 1)
include/asm-arm/arch-epxa10db/memory.h deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/include/asm-arm/arch-epxa10/memory.h
*
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET UL(0x00000000)
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
#define __virt_to_bus(x) (x - PAGE_OFFSET + /*SDRAM_BASE*/0)
#define __bus_to_virt(x) (x - /*SDRAM_BASE*/0 + PAGE_OFFSET)
#endif
include/asm-arm/arch-epxa10db/mode_ctrl00.h deleted 100644 → 0
View file @ b9abaa3f
#ifndef __MODE_CTRL00_H
#define __MODE_CTRL00_H
/*
* Register definitions for the reset and mode control
*/
/*
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR ))
#define BOOT_CR_BF_MSK (0x1)
#define BOOT_CR_BF_OFST (0)
#define BOOT_CR_HM_MSK (0x2)
#define BOOT_CR_HM_OFST (1)
#define BOOT_CR_RE_MSK (0x4)
#define BOOT_CR_RE_OFST (2)
#define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x4 ))
#define RESET_SR_WR_MSK (0x1)
#define RESET_SR_WR_OFST (0)
#define RESET_SR_CR_MSK (0x2)
#define RESET_SR_CR_OFST (1)
#define RESET_SR_JT_MSK (0x4)
#define RESET_SR_JT_OFST (2)
#define RESET_SR_ER_MSK (0x8)
#define RESET_SR_ER_OFST (3)
#define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x08 ))
#define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x20 ))
#define SRAM0_SR_SIZE_MSK (0xFFFFF000)
#define SRAM0_SR_SIZE_OFST (12)
#define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x24 ))
#define SRAM1_SR_SIZE_MSK (0xFFFFF000)
#define SRAM1_SR_SIZE_OFST (12)
#define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x30 ))
#define DPSRAM0_SR_MODE_MSK (0xF)
#define DPSRAM0_SR_MODE_OFST (0)
#define DPSRAM0_SR_GLBL_MSK (0x30)
#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000)
#define DPSRAM0_SR_SIZE_OFST (12)
#define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x34 ))
#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0)
#define DPSRAM0_LCR_LCKADDR_OFST (4)
#define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x38 ))
#define DPSRAM1_SR_MODE_MSK (0xF)
#define DPSRAM1_SR_MODE_OFST (0)
#define DPSRAM1_SR_GLBL_MSK (0x30)
#define DPSRAM1_SR_GLBL_OFST (4)
#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000)
#define DPSRAM1_SR_SIZE_OFST (12)
#define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x3C ))
#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0)
#define DPSRAM1_LCR_LCKADDR_OFST (4)
#endif /* __MODE_CTRL00_H */
include/asm-arm/arch-epxa10db/param.h deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/include/asm-arm/arch-epxa10db/param.h
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
include/asm-arm/arch-epxa10db/platform.h deleted 100644 → 0
View file @ b9abaa3f
#ifndef PLATFORM_H
#define PLATFORM_H
#include "excalibur.h"
#define MAXIRQNUM 15
#endif
include/asm-arm/arch-epxa10db/pld_conf00.h deleted 100644 → 0
View file @ b9abaa3f
#ifndef __PLD_CONF00_H
#define __PLD_CONF00_H
/*
* Register definitions for the PLD Configuration Logic
*/
/*
*
* This file contains the register definitions for the Excalibur
* Interrupt controller INT_CTRL00.
*
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define CONFIG_CONTROL(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR))
#define CONFIG_CONTROL_LK_MSK (0x1)
#define CONFIG_CONTROL_LK_OFST (0)
#define CONFIG_CONTROL_CO_MSK (0x2)
#define CONFIG_CONTROL_CO_OFST (1)
#define CONFIG_CONTROL_B_MSK (0x4)
#define CONFIG_CONTROL_B_OFST (2)
#define CONFIG_CONTROL_PC_MSK (0x8)
#define CONFIG_CONTROL_PC_OFST (3)
#define CONFIG_CONTROL_E_MSK (0x10)
#define CONFIG_CONTROL_E_OFST (4)
#define CONFIG_CONTROL_ES_MSK (0xE0)
#define CONFIG_CONTROL_ES_OFST (5)
#define CONFIG_CONTROL_ES_0_MSK (0x20)
#define CONFIG_CONTROL_ES_1_MSK (0x40)
#define CONFIG_CONTROL_ES_2_MSK (0x80)
#define CONFIG_CONTROL_CLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x4 ))
#define CONFIG_CONTROL_CLOCK_RATIO_MSK (0xFFFF)
#define CONFIG_CONTROL_CLOCK_RATIO_OFST (0)
#define CONFIG_CONTROL_DATA(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x8 ))
#define CONFIG_CONTROL_DATA_MSK (0xFFFFFFFF)
#define CONFIG_CONTROL_DATA_OFST (0)
#define CONFIG_UNLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0xC ))
#define CONFIG_UNLOCK_MSK (0xFFFFFFFF)
#define CONFIG_UNLOCK_OFST (0)
#define CONFIG_UNLOCK_MAGIC (0x554E4C4B)
#endif /* __PLD_CONF00_H */
include/asm-arm/arch-epxa10db/system.h deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/include/asm-arm/arch-epxa10db/system.h
*
* Copyright (C) 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/arch/platform.h>
static inline void arch_idle(void)
{
/*
* This should do all the clock switching
* and wait for interrupt tricks
*/
cpu_do_idle();
}
extern __inline__ void arch_reset(char mode)
{
/* Hmm... We can probably do something with the watchdog... */
}
#endif
include/asm-arm/arch-epxa10db/tdkphy.h deleted 100644 → 0
View file @ b9abaa3f
This diff is collapsed.
include/asm-arm/arch-epxa10db/timer00.h deleted 100644 → 0
View file @ b9abaa3f
/*
*
* This file contains the register definitions for the Excalibur
* Timer TIMER00.
*
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __TIMER00_H
#define __TIMER00_H
/*
* Register definitions for the timers
*/
#define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 ))
#define TIMER0_CR_B_MSK (0x20)
#define TIMER0_CR_B_OFST (0x5)
#define TIMER0_CR_S_MSK (0x10)
#define TIMER0_CR_S_OFST (0x4)
#define TIMER0_CR_CI_MSK (0x08)
#define TIMER0_CR_CI_OFST (0x3)
#define TIMER0_CR_IE_MSK (0x04)
#define TIMER0_CR_IE_OFST (0x2)
#define TIMER0_CR_MODE_MSK (0x3)
#define TIMER0_CR_MODE_OFST (0)
#define TIMER0_CR_MODE_FREE (0)
#define TIMER0_CR_MODE_ONE (1)
#define TIMER0_CR_MODE_INTVL (2)
#define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 ))
#define TIMER0_SR_B_MSK (0x20)
#define TIMER0_SR_B_OFST (0x5)
#define TIMER0_SR_S_MSK (0x10)
#define TIMER0_SR_S_OFST (0x4)
#define TIMER0_SR_CI_MSK (0x08)
#define TIMER0_SR_CI_OFST (0x3)
#define TIMER0_SR_IE_MSK (0x04)
#define TIMER0_SR_IE_OFST (0x2)
#define TIMER0_SR_MODE_MSK (0x3)
#define TIMER0_SR_MODE_OFST (0)
#define TIMER0_SR_MODE_FREE (0)
#define TIMER0_SR_MODE_ONE (1)
#define TIMER0_SR_MODE_INTVL (2)
#define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x010 ))
#define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x020 ))
#define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x030 ))
#define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 ))
#define TIMER1_CR_B_MSK (0x20)
#define TIMER1_CR_B_OFST (0x5)
#define TIMER1_CR_S_MSK (0x10)
#define TIMER1_CR_S_OFST (0x4)
#define TIMER1_CR_CI_MSK (0x08)
#define TIMER1_CR_CI_OFST (0x3)
#define TIMER1_CR_IE_MSK (0x04)
#define TIMER1_CR_IE_OFST (0x2)
#define TIMER1_CR_MODE_MSK (0x3)
#define TIMER1_CR_MODE_OFST (0)
#define TIMER1_CR_MODE_FREE (0)
#define TIMER1_CR_MODE_ONE (1)
#define TIMER1_CR_MODE_INTVL (2)
#define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 ))
#define TIMER1_SR_B_MSK (0x20)
#define TIMER1_SR_B_OFST (0x5)
#define TIMER1_SR_S_MSK (0x10)
#define TIMER1_SR_S_OFST (0x4)
#define TIMER1_SR_CI_MSK (0x08)
#define TIMER1_SR_CI_OFST (0x3)
#define TIMER1_SR_IE_MSK (0x04)
#define TIMER1_SR_IE_OFST (0x2)
#define TIMER1_SR_MODE_MSK (0x3)
#define TIMER1_SR_MODE_OFST (0)
#define TIMER1_SR_MODE_FREE (0)
#define TIMER1_SR_MODE_ONE (1)
#define TIMER1_SR_MODE_INTVL (2)
#define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x050 ))
#define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x060 ))
#define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x070 ))
#endif /* __TIMER00_H */
include/asm-arm/arch-epxa10db/timex.h deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/include/asm-arm/arch-epxa10db/timex.h
*
* Excalibur timex specifications
*
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* ??
*/
#define CLOCK_TICK_RATE (50000000 / 16)
include/asm-arm/arch-epxa10db/uart00.h deleted 100644 → 0
View file @ b9abaa3f
/* *
* Copyright (C) 2001 Altera Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __UART00_H
#define __UART00_H
/*
* Register definitions for the UART
*/
#define UART_TX_FIFO_SIZE (15)
#define UART_RSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x00 ))
#define UART_RSR_RX_LEVEL_MSK (0x1f)
#define UART_RSR_RX_LEVEL_OFST (0)
#define UART_RSR_RE_MSK (0x80)
#define UART_RSR_RE_OFST (7)
#define UART_RDS(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x04 ))
#define UART_RDS_BI_MSK (0x8)
#define UART_RDS_BI_OFST (4)
#define UART_RDS_FE_MSK (0x4)
#define UART_RDS_FE_OFST (2)
#define UART_RDS_PE_MSK (0x2)
#define UART_RDS_PE_OFST (1)
#define UART_RDS_OE_MSK (0x1)
#define UART_RDS_OE_OFST (0)
#define UART_RD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x08 ))
#define UART_RD_RX_DATA_MSK (0xff)
#define UART_RD_RX_DATA_OFST (0)
#define UART_TSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x0c ))
#define UART_TSR_TX_LEVEL_MSK (0x1f)
#define UART_TSR_TX_LEVEL_OFST (0)
#define UART_TSR_TXI_MSK (0x80)
#define UART_TSR_TXI_OFST (7)
#define UART_TD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x10 ))
#define UART_TD_TX_DATA_MSK (0xff)
#define UART_TD_TX_DATA_OFST (0)
#define UART_FCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x14 ))
#define UART_FCR_RX_THR_MSK (0xd0)
#define UART_FCR_RX_THR_OFST (5)
#define UART_FCR_RX_THR_1 (0x00)
#define UART_FCR_RX_THR_2 (0x20)
#define UART_FCR_RX_THR_4 (0x40)
#define UART_FCR_RX_THR_6 (0x60)
#define UART_FCR_RX_THR_8 (0x80)
#define UART_FCR_RX_THR_10 (0xa0)
#define UART_FCR_RX_THR_12 (0xc0)
#define UART_FCR_RX_THR_14 (0xd0)
#define UART_FCR_TX_THR_MSK (0x1c)
#define UART_FCR_TX_THR_OFST (2)
#define UART_FCR_TX_THR_0 (0x00)
#define UART_FCR_TX_THR_2 (0x04)
#define UART_FCR_TX_THR_4 (0x08)
#define UART_FCR_TX_THR_8 (0x0c)
#define UART_FCR_TX_THR_10 (0x10)
#define UART_FCR_TX_THR_12 (0x14)
#define UART_FCR_TX_THR_14 (0x18)
#define UART_FCR_TX_THR_15 (0x1c)
#define UART_FCR_RC_MSK (0x02)
#define UART_FCR_RC_OFST (1)
#define UART_FCR_TC_MSK (0x01)
#define UART_FCR_TC_OFST (0)
#define UART_IES(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x18 ))
#define UART_IES_ME_MSK (0x8)
#define UART_IES_ME_OFST (3)
#define UART_IES_TIE_MSK (0x4)
#define UART_IES_TIE_OFST (2)
#define UART_IES_TE_MSK (0x2)
#define UART_IES_TE_OFST (1)
#define UART_IES_RE_MSK (0x1)
#define UART_IES_RE_OFST (0)
#define UART_IEC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x1c ))
#define UART_IEC_ME_MSK (0x8)
#define UART_IEC_ME_OFST (3)
#define UART_IEC_TIE_MSK (0x4)
#define UART_IEC_TIE_OFST (2)
#define UART_IEC_TE_MSK (0x2)
#define UART_IEC_TE_OFST (1)
#define UART_IEC_RE_MSK (0x1)
#define UART_IEC_RE_OFST (0)
#define UART_ISR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x20 ))
#define UART_ISR_MI_MSK (0x8)
#define UART_ISR_MI_OFST (3)
#define UART_ISR_TII_MSK (0x4)
#define UART_ISR_TII_OFST (2)
#define UART_ISR_TI_MSK (0x2)
#define UART_ISR_TI_OFST (1)
#define UART_ISR_RI_MSK (0x1)
#define UART_ISR_RI_OFST (0)
#define UART_IID(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x24 ))
#define UART_IID_IID_MSK (0x7)
#define UART_IID_IID_OFST (0)
#define UART_MC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x28 ))
#define UART_MC_OE_MSK (0x40)
#define UART_MC_OE_OFST (6)
#define UART_MC_SP_MSK (0x20)
#define UART_MC_SP_OFST (5)
#define UART_MC_EP_MSK (0x10)
#define UART_MC_EP_OFST (4)
#define UART_MC_PE_MSK (0x08)
#define UART_MC_PE_OFST (3)
#define UART_MC_ST_MSK (0x04)
#define UART_MC_ST_ONE (0x0)
#define UART_MC_ST_TWO (0x04)
#define UART_MC_ST_OFST (2)
#define UART_MC_CLS_MSK (0x03)
#define UART_MC_CLS_OFST (0)
#define UART_MC_CLS_CHARLEN_5 (0)
#define UART_MC_CLS_CHARLEN_6 (1)
#define UART_MC_CLS_CHARLEN_7 (2)
#define UART_MC_CLS_CHARLEN_8 (3)
#define UART_MCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x2c ))
#define UART_MCR_AC_MSK (0x80)
#define UART_MCR_AC_OFST (7)
#define UART_MCR_AR_MSK (0x40)
#define UART_MCR_AR_OFST (6)
#define UART_MCR_BR_MSK (0x20)
#define UART_MCR_BR_OFST (5)
#define UART_MCR_LB_MSK (0x10)
#define UART_MCR_LB_OFST (4)
#define UART_MCR_DCD_MSK (0x08)
#define UART_MCR_DCD_OFST (3)
#define UART_MCR_RI_MSK (0x04)
#define UART_MCR_RI_OFST (2)
#define UART_MCR_DTR_MSK (0x02)
#define UART_MCR_DTR_OFST (1)
#define UART_MCR_RTS_MSK (0x01)
#define UART_MCR_RTS_OFST (0)
#define UART_MSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x30 ))
#define UART_MSR_DCD_MSK (0x80)
#define UART_MSR_DCD_OFST (7)
#define UART_MSR_RI_MSK (0x40)
#define UART_MSR_RI_OFST (6)
#define UART_MSR_DSR_MSK (0x20)
#define UART_MSR_DSR_OFST (5)
#define UART_MSR_CTS_MSK (0x10)
#define UART_MSR_CTS_OFST (4)
#define UART_MSR_DDCD_MSK (0x08)
#define UART_MSR_DDCD_OFST (3)
#define UART_MSR_TERI_MSK (0x04)
#define UART_MSR_TERI_OFST (2)
#define UART_MSR_DDSR_MSK (0x02)
#define UART_MSR_DDSR_OFST (1)
#define UART_MSR_DCTS_MSK (0x01)
#define UART_MSR_DCTS_OFST (0)
#define UART_DIV_LO(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x34 ))
#define UART_DIV_LO_DIV_MSK (0xff)
#define UART_DIV_LO_DIV_OFST (0)
#define UART_DIV_HI(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x38 ))
#define UART_DIV_HI_DIV_MSK (0xff)
#define UART_DIV_HI_DIV_OFST (0)
#endif /* __UART00_H */
include/asm-arm/arch-epxa10db/uncompress.h deleted 100644 → 0
View file @ b9abaa3f
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include/asm-arm/arch-epxa10db/vmalloc.h deleted 100644 → 0
View file @ b9abaa3f
/*
* linux/include/asm-arm/arch-epxa10db/vmalloc.h
*
* Copyright (C) 2000 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
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